From b2e6dabee765471986b3460a1193467a76893b67 Mon Sep 17 00:00:00 2001 From: Phanindra Babu Pabba Date: Thu, 11 Feb 2021 20:28:40 +0530 Subject: [PATCH] ARM: dts: msm: Enable qseecom on sdxnightjar Add device tree entries to enable qseecom on sdxnightjar target. Change-Id: I50059575733e14b0935b68f42a01c409a34650ba --- qcom/sdxnightjar-ion.dtsi | 12 ++++++++++++ qcom/sdxnightjar.dtsi | 40 +++++++++++++++++++++++++++++++-------- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi index 177423c67e8a..173d5c56a634 100644 --- a/qcom/sdxnightjar-ion.dtsi +++ b/qcom/sdxnightjar-ion.dtsi @@ -16,6 +16,18 @@ memory-region = <&audio_mem>; qcom,ion-heap-type = "DMA"; }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 95eeafc47ad1..ba8c1d9387b7 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -53,6 +53,22 @@ label = "mss_mem"; }; + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x400000>; + }; + dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; @@ -75,6 +91,10 @@ compatible = "qcom,scm"; qcom,dload-mode = <&tcsr 0x6100>; }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; }; cpus { @@ -560,19 +580,23 @@ compatible = "qcom,qseecom"; reg = <0x87800000 0x200000>; reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; - qcom,msm-bus,name = "qseecom-noc"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <47 512 0 0>, - <47 512 200000 400000>, - <47 512 300000 800000>, - <47 512 400000 1000000>; + qcom,qsee-reentrancy-support = <2>; + qcom,support-bus-scaling; + qcom,appsbl-qseecom-support; + interconnect-names = "data_path"; + interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>; /*TODO: Fix the clock when tree is available*/ clock-names = "core_clk", "iface_clk", "bus_clk","core_clk_src"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; qcom,ce-opp-freq = <100000000>; };