A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Add cpufreq-hw node for Lahaina"

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qctecmdr 2020-01-14 03:14:47 -08:00 • committed by Gerrit - the friendly Code Review server
commit 7fc330a26d
1 changed files with 24 additions and 0 deletions
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24
qcom/lahaina.dtsi
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@ -50,6 +50,7 @@
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
@ -75,6 +76,7 @@
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
@ -94,6 +96,7 @@
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
@ -113,6 +116,7 @@
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
@ -132,6 +136,7 @@
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
@ -151,6 +156,7 @@
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
@ -170,6 +176,7 @@
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
@ -189,6 +196,7 @@
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
capacity-dmips-mhz = <2048>;
dynamic-power-coefficient = <845>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
@ -790,6 +798,22 @@
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
<0x18593000 0x1000>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
#freq-domain-cells = <2>;
};
/* CAM_CC GDSCs */
cam_cc_bps_gdsc: qcom,gdsc@ad07004 {
compatible = "qcom,gdsc";