From 805620e0ea5dea0460cf33e08a431f96b7c9003b Mon Sep 17 00:00:00 2001
From: chailu1 <chailu1@lenovo.com>
Date: Fri, 3 Sep 2021 16:18:40 +0800
Subject: [PATCH] arm/dts: Modify trip soc  threshold from 10 to 5 for corfur

Modify trip soc limiting cpu performance threshold
from 10 to 5 for corfur product.

Change-Id: If4a551d49ea34bde4596d35cad04f6975611bfbc
Signed-off-by: chailu1 <chailu1@lenovo.com>
Reviewed-on: https://gerrit.mot.com/2057460
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
---
 qcom/blair-pm6125-moto-common-overlay.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/qcom/blair-pm6125-moto-common-overlay.dtsi b/qcom/blair-pm6125-moto-common-overlay.dtsi
index 628aa6a12b1f..f3e847ead1f6 100644
--- a/qcom/blair-pm6125-moto-common-overlay.dtsi
+++ b/qcom/blair-pm6125-moto-common-overlay.dtsi
@@ -308,3 +308,7 @@
 	io-channel-names = "usb_hw_current_max";
 	qcom,bcl-not-mitigate-icl = <2500>;
 };
+
+&socd_trip {
+       temperature = <95>;
+};