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mm/mmu_gather: invalidate TLB correctly on batch allocation failure and flush

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commit 0ed1325967ab5f7a4549a2641c6ebe115f76e228 upstream.

Architectures for which we have hardware walkers of Linux page table
should flush TLB on mmu gather batch allocation failures and batch flush.
Some architectures like POWER supports multiple translation modes (hash
and radix) and in the case of POWER only radix translation mode needs the
above TLBI.  This is because for hash translation mode kernel wants to
avoid this extra flush since there are no hardware walkers of linux page
table.  With radix translation, the hardware also walks linux page table
and with that, kernel needs to make sure to TLB invalidate page walk cache
before page table pages are freed.

More details in commit d86564a2f0 ("mm/tlb, x86/mm: Support invalidating
TLB caches for RCU_TABLE_FREE")

The changes to sparc are to make sure we keep the old behavior since we
are now removing HAVE_RCU_TABLE_NO_INVALIDATE.  The default value for
tlb_needs_table_invalidate is to always force an invalidate and sparc can
avoid the table invalidate.  Hence we define tlb_needs_table_invalidate to
false for sparc architecture.

Link: http://lkml.kernel.org/r/[email protected]
Fixes: a46cc7a90f ("powerpc/mm/radix: Improve TLB/PWC flushes")
Signed-off-by: Peter Zijlstra (Intel) <[email protected]
Signed-off-by: Aneesh Kumar K.V <[email protected]>
Acked-by: Michael Ellerman <[email protected]>	[powerpc]
Cc: <[email protected]>	[4.14+]
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Peter Zijlstra 2020-02-03 17:36:49 -08:00 • committed by Greg Kroah-Hartman
commit 806cabd311
7 changed files with 43 additions and 20 deletions
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1
arch/sparc/Kconfig
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@ -65,7 +65,6 @@ config SPARC64
select HAVE_KRETPROBES
select HAVE_KPROBES
select HAVE_RCU_TABLE_FREE if SMP
select HAVE_RCU_TABLE_NO_INVALIDATE if HAVE_RCU_TABLE_FREE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_ARCH_TRANSPARENT_HUGEPAGE
select HAVE_DYNAMIC_FTRACE

9
arch/sparc/include/asm/tlb_64.h
View file

@ -28,6 +28,15 @@ void flush_tlb_pending(void);
#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
#define tlb_flush(tlb) flush_tlb_pending()
/*
* SPARC64's hardware TLB fill does not use the Linux page-tables
* and therefore we don't need a TLBI when freeing page-table pages.
*/
#ifdef CONFIG_HAVE_RCU_TABLE_FREE
#define tlb_needs_table_invalidate() (false)
#endif
#include <asm-generic/tlb.h>
#endif /* _SPARC64_TLB_H */