From 3d0293056f81f2464379e52dcd41d85a5ce0994d Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 25 Feb 2021 12:15:07 +0530 Subject: [PATCH] ARM: dts: msm: Base device tree of SA6155 GVM Add base device tree of Sa6155 guest. Change-Id: I22ca9e59e8a4ddb2ae0a891814739eef4491aae5 --- qcom/Makefile | 3 +- qcom/sa6155p-vm-la.dts | 11 + qcom/sa6155p-vm-la.dtsi | 35 ++++ qcom/sa6155p-vm-pcie.dtsi | 249 +++++++++++++++++++++++ qcom/sa6155p-vm-usb.dtsi | 412 ++++++++++++++++++++++++++++++++++++++ qcom/sa6155p-vm.dtsi | 327 ++++++++++++++++++++++++++++++ 6 files changed, 1036 insertions(+), 1 deletion(-) create mode 100644 qcom/sa6155p-vm-la.dts create mode 100644 qcom/sa6155p-vm-la.dtsi create mode 100644 qcom/sa6155p-vm-pcie.dtsi create mode 100644 qcom/sa6155p-vm-usb.dtsi create mode 100644 qcom/sa6155p-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index c4fca42071c6..f99706b3ea28 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -346,7 +346,8 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8195-vm-lv.dtb \ sa8195-vm-la-mt.dtb \ sa8195-vm-lv-mt.dtb \ - sa8195-vm-lv-lxc.dtb + sa8195-vm-lv-lxc.dtb \ + sa6155p-vm-la.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/qcom/sa6155p-vm-la.dts b/qcom/sa6155p-vm-la.dts new file mode 100644 index 000000000000..f8c2d8176bab --- /dev/null +++ b/qcom/sa6155p-vm-la.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa6155p-vm.dtsi" +#include "sa6155p-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; + compatible = "qcom,sa6155p"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0x1000001 0>; +}; diff --git a/qcom/sa6155p-vm-la.dtsi b/qcom/sa6155p-vm-la.dtsi new file mode 100644 index 000000000000..96e830bab203 --- /dev/null +++ b/qcom/sa6155p-vm-la.dtsi @@ -0,0 +1,35 @@ +&reserved_memory { + pmem_shared: pmem_shared_region@a1600000 { + reg = <0x0 0xa1600000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; + +}; + +&usb0 { + status = "ok"; +}; + +&qusb_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa6155p-vm-pcie.dtsi b/qcom/sa6155p-vm-pcie.dtsi new file mode 100644 index 000000000000..406b50e5a14f --- /dev/null +++ b/qcom/sa6155p-vm-pcie.dtsi @@ -0,0 +1,249 @@ +#include +#include + +&soc { + pcie0: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0070 0x0f 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0194 0x06 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x35 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x04 0x0 + 0x0084 0x16 0x0 + 0x0090 0x30 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x00a8 0x01 0x0 + 0x000c 0x0a 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x09b0 0x07 0x0 + 0x09d8 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 101 0>; + wake-gpio = <&tlmm 100 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&L12A>; + vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0p9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + + qcom,bw-scale = ; + + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + msi-parent = <&pcie0_msi>; + + qcom,max-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + qcom,core-preset = <0x77777777>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2609>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + status = "disabled"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:010a"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + status = "disabled"; + }; +}; diff --git a/qcom/sa6155p-vm-usb.dtsi b/qcom/sa6155p-vm-usb.dtsi new file mode 100644 index 000000000000..9fc20ab70033 --- /dev/null +++ b/qcom/sa6155p-vm-usb.dtsi @@ -0,0 +1,412 @@ +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "bypass"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <61>; + + qcom,ignore-wakeup-src-in-hostmode; + + + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupts = ; + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + usbbam: qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + status = "disabled"; + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e2000 0x180>, + <0x01fcb250 0x4>, + <0x007801f8 0x4>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@88e6000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x88e6000 0x1000>, + <0x01fcb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&L5A>; + core-supply = <&L12A>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xb4 0x00 0x00 + 0xb8 0x08 0x00 + 0x70 0x0f 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x194 0x06 0x00 + 0x100 0x80 0x00 + 0xa8 0x01 0x00 + 0x430 0x0b 0x00 + 0x830 0x0b 0x00 + 0x444 0x00 0x00 + 0x844 0x00 0x00 + 0x43c 0x00 0x00 + 0x83c 0x00 0x00 + 0x440 0x00 0x00 + 0x840 0x00 0x00 + 0x408 0x0a 0x00 + 0x808 0x0a 0x00 + 0x414 0x06 0x00 + 0x814 0x06 0x00 + 0x434 0x75 0x00 + 0x834 0x75 0x00 + 0x4d4 0x02 0x00 + 0x8d4 0x02 0x00 + 0x4d8 0x4e 0x00 + 0x8d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x8dc 0x18 0x00 + 0x4f8 0x77 0x00 + 0x8f8 0x77 0x00 + 0x4fc 0x80 0x00 + 0x8fc 0x80 0x00 + 0x4c0 0x0a 0x00 + 0x8c0 0x0a 0x00 + 0x504 0x03 0x00 + 0x904 0x03 0x00 + 0x50c 0x16 0x00 + 0x90c 0x16 0x00 + 0x500 0x00 0x00 + 0x900 0x00 0x00 + 0x564 0x00 0x00 + 0x964 0x00 0x00 + 0x260 0x10 0x00 + 0x660 0x10 0x00 + 0x2a4 0x12 0x00 + 0x6a4 0x12 0x00 + 0x28c 0xc6 0x00 + 0x68c 0xc6 0x00 + 0x244 0x00 0x00 + 0x644 0x00 0x00 + 0x248 0x00 0x00 + 0x648 0x00 0x00 + 0xc0c 0x9f 0x00 + 0xc24 0x17 0x00 + 0xc28 0x0f 0x00 + 0xcc8 0x83 0x00 + 0xcc4 0x02 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x85 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xcb8 0x75 0x00 + 0xcbc 0x13 0x00 + 0xcb0 0x86 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + status = "disabled"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x172f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: hsusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb20_sec_gdsc>; + clocks = <&gcc GCC_USB20_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB20_SEC_SLEEP_CLK>, + <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB20_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xcd00>; + interrupts = ; + usb-phy = <&qusb_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + qusb_phy1: qusb@88e3000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e3000 0x180>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + qcom,hold-reset; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + +}; + + + diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi new file mode 100644 index 000000000000..e00c1fdc6f3d --- /dev/null +++ b/qcom/sa6155p-vm.dtsi @@ -0,0 +1,327 @@ +#include +#include +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; + qcom,msm-name = "SA6155P"; + qcom,msm-id = <377 0x0>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <347>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <347>; + }; + + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x4>; + capacity-dmips-mhz = <347>; + }; + + CPU5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x5>; + capacity-dmips-mhz = <347>; + }; + + CPU6: cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x6>; + capacity-dmips-mhz = <347>; + }; + + CPU7: cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x7>; + capacity-dmips-mhz = <347>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + + core2 { + cpu = <&CPU4>; + }; + + core3 { + cpu = <&CPU5>; + }; + + core4 { + cpu = <&CPU6>; + }; + + core5 { + cpu = <&CPU7>; + }; + }; + }; + }; +}; + + +&soc { + VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL: + pm6155_1_s2_level: regulator-pm6155-1-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_s2_level"; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000>, + <0x150c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "km_clk_src"; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm6150-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <6 486 1>, <8 488 4>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; +}; + +®ulator { + usb30_prim_gdsc: usb30_prim_gdsc { + regulator-name = "usb30_prim_gdsc"; + }; + + usb20_sec_gdsc: usb20_sec_gdsc { + regulator-name = "usb20_sec_gdsc"; + }; + + pcie_0_gdsc: pcie_0_gdsc { + regulator-name = "pcie_0_gdsc"; + }; + + L2A: pm6155_1_l2: regulator-pm6155-1-l2 { + regulator-name = "ldoa2"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + }; + + L5A: pm6155_1_l5: regulator-pm6155-1-l5 { + regulator-name = "ldoa5"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + L10A: pm6155_1_l10: regulator-pm6155-1-l10 { + regulator-name = "ldoa10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + }; + + L12A: pm6155_1_l12: regulator-pm6155-1-l12 { + regulator-name = "ldoa12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + }; + + L13A: pm6155_1_l13: regulator-pm6155-1-l13 { + regulator-name = "ldoa13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + }; + + S6A: pm6155_1_s6: regulator-pm6155-1-s6 { + regulator-name = "smpa6"; + regulator-min-microvolt = <947000>; + regulator-max-microvolt = <1404000>; + }; + + S5A: pm6155_1_s5: regulator-pm6155-1-s5 { + regulator-name = "smpa5"; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + }; + + L15A: pm6155_1_l15: regulator-pm6155-1-l15 { + regulator-name = "ldoa15"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <1904000>; + }; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + +#include "sm6150-pinctrl.dtsi" +#include "sa6155p-vm-usb.dtsi" +#include "sa6155p-vm-pcie.dtsi" +#include "sm6150-qupv3.dtsi" + +&tlmm { + /delete-property/ wakeup-parent; +}; + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; +