mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 22:40:54 -04:00
Merge "arm64: defconfig: Enable gcc clock driver for Lahaina"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
81b7681939
5 changed files with 3831 additions and 231 deletions
1
arch/arm64/configs/vendor/lahaina_GKI.config
vendored
1
arch/arm64/configs/vendor/lahaina_GKI.config
vendored
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@ -34,3 +34,4 @@ CONFIG_MSM_PIL_SSR_GENERIC=m
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CONFIG_MSM_SERVICE_LOCATOR=m
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CONFIG_MSM_SERVICE_NOTIFIER=m
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CONFIG_REGULATOR_RPMH=m
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CONFIG_MSM_GCC_LAHAINA=m
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@ -333,4 +333,12 @@ config MSM_CLK_AOP_QMP
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Say Y to support the clocks managed by AOP on platforms such as
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sdm845.
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config MSM_GCC_LAHAINA
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tristate "LAHAINA Global Clock Controller"
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depends on COMMON_CLK_QCOM
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help
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Support for the global clock controller on Qualcomm Technologies, Inc
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LAHAINA devices.
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Say Y if you want to use peripheral devices such as UART, SPI, I2C,
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USB, UFS, SD/eMMC, PCIe, etc.
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endif
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@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
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obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
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obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
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obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
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obj-$(CONFIG_MSM_GCC_LAHAINA) += gcc-lahaina.o
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obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
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3600
drivers/clk/qcom/gcc-lahaina.c
Normal file
3600
drivers/clk/qcom/gcc-lahaina.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -7,240 +7,230 @@
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#define _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H
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/* GCC clocks */
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#define CORE_BI_PLL_TEST_SE 0
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 1
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 2
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#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 3
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 4
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 5
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 7
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#define GCC_BOOT_ROM_AHB_CLK 8
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#define GCC_CAMERA_AHB_CLK 9
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#define GCC_CAMERA_HF_AXI_CLK 10
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#define GCC_CAMERA_SF_AXI_CLK 11
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#define GCC_CAMERA_XO_CLK 12
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 13
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 14
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#define GCC_CPUSS_AHB_CLK 15
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#define GCC_CPUSS_AHB_CLK_SRC 16
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 17
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#define GCC_DDRSS_GPU_AXI_CLK 18
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#define GCC_DDRSS_PCIE_SF_TBU_CLK 19
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#define GCC_DISP_AHB_CLK 20
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#define GCC_DISP_HF_AXI_CLK 21
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#define GCC_DISP_SF_AXI_CLK 22
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#define GCC_DISP_XO_CLK 23
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#define GCC_DPM_CB_CLK 24
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#define GCC_DPM_CLK 25
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#define GCC_DPM_CLK_SRC 26
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#define GCC_DPM_CX_AHB_CLK 27
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#define GCC_DPM_MX_AHB_CLK 28
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#define GCC_GP1_CLK 29
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#define GCC_GP1_CLK_SRC 30
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#define GCC_GP2_CLK 31
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#define GCC_GP2_CLK_SRC 32
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#define GCC_GP3_CLK 33
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#define GCC_GP3_CLK_SRC 34
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#define GCC_GPLL0 35
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#define GCC_GPLL0_OUT_EVEN 36
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#define GCC_GPLL9 37
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#define GCC_GPU_CFG_AHB_CLK 38
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#define GCC_GPU_GPLL0_CLK_SRC 39
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 40
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#define GCC_GPU_IREF_EN 41
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#define GCC_GPU_MEMNOC_GFX_CLK 42
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#define GCC_GPU_SNOC_DVM_GFX_CLK 43
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#define GCC_PCIE0_PHY_RCHNG_CLK 44
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#define GCC_PCIE1_PHY_RCHNG_CLK 45
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#define GCC_PCIE_0_AUX_CLK 46
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#define GCC_PCIE_0_AUX_CLK_SRC 47
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#define GCC_PCIE_0_CFG_AHB_CLK 48
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#define GCC_PCIE_0_CLKREF_EN 49
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#define GCC_PCIE_0_MSTR_AXI_CLK 50
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51
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#define GCC_PCIE_0_PIPE_CLK 52
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#define GCC_PCIE_0_SLV_AXI_CLK 53
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 54
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#define GCC_PCIE_1_AUX_CLK 55
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#define GCC_PCIE_1_AUX_CLK_SRC 56
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#define GCC_PCIE_1_CFG_AHB_CLK 57
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#define GCC_PCIE_1_CLKREF_EN 58
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#define GCC_PCIE_1_MSTR_AXI_CLK 59
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 60
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#define GCC_PCIE_1_PIPE_CLK 61
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#define GCC_PCIE_1_SLV_AXI_CLK 62
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63
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#define GCC_PDM2_CLK 64
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#define GCC_PDM2_CLK_SRC 65
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#define GCC_PDM_AHB_CLK 66
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#define GCC_PDM_XO4_CLK 67
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 68
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 69
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#define GCC_QMIP_DISP_AHB_CLK 70
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 71
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 72
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73
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#define GCC_QUPV3_WRAP0_CORE_CLK 74
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#define GCC_QUPV3_WRAP0_S0_CLK 75
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76
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#define GCC_QUPV3_WRAP0_S1_CLK 77
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78
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#define GCC_QUPV3_WRAP0_S2_CLK 79
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80
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#define GCC_QUPV3_WRAP0_S3_CLK 81
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82
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#define GCC_QUPV3_WRAP0_S4_CLK 83
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84
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#define GCC_QUPV3_WRAP0_S5_CLK 85
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86
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#define GCC_QUPV3_WRAP0_S6_CLK 87
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 88
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#define GCC_QUPV3_WRAP0_S7_CLK 89
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 90
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 91
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#define GCC_QUPV3_WRAP1_CORE_CLK 92
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#define GCC_QUPV3_WRAP1_S0_CLK 93
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 94
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#define GCC_QUPV3_WRAP1_S1_CLK 95
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 96
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#define GCC_QUPV3_WRAP1_S2_CLK 97
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 98
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#define GCC_QUPV3_WRAP1_S3_CLK 99
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 100
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#define GCC_QUPV3_WRAP1_S4_CLK 101
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 102
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#define GCC_QUPV3_WRAP1_S5_CLK 103
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 104
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 105
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#define GCC_QUPV3_WRAP2_CORE_CLK 106
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#define GCC_QUPV3_WRAP2_S0_CLK 107
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 108
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#define GCC_QUPV3_WRAP2_S1_CLK 109
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 110
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#define GCC_QUPV3_WRAP2_S2_CLK 111
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 112
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#define GCC_QUPV3_WRAP2_S3_CLK 113
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 114
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#define GCC_QUPV3_WRAP2_S4_CLK 115
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 116
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#define GCC_QUPV3_WRAP2_S5_CLK 117
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 118
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 121
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 122
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 123
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 124
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#define GCC_SDCC2_AHB_CLK 125
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#define GCC_SDCC2_APPS_CLK 126
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#define GCC_SDCC2_APPS_CLK_SRC 127
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#define GCC_SDCC4_AHB_CLK 128
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#define GCC_SDCC4_APPS_CLK 129
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#define GCC_SDCC4_APPS_CLK_SRC 130
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 131
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#define GCC_UFS_1_CLKREF_EN 132
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#define GCC_UFS_CARD_AHB_CLK 133
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#define GCC_UFS_CARD_AXI_CLK 134
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#define GCC_UFS_CARD_AXI_CLK_SRC 135
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#define GCC_UFS_CARD_AXI_HW_CTL_CLK 136
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#define GCC_UFS_CARD_ICE_CORE_CLK 137
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 138
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#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 139
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#define GCC_UFS_CARD_PHY_AUX_CLK 140
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 141
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#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 142
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 143
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 144
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 145
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 146
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 147
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#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 148
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#define GCC_UFS_PHY_AHB_CLK 149
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#define GCC_UFS_PHY_AXI_CLK 150
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#define GCC_UFS_PHY_AXI_CLK_SRC 151
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 152
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#define GCC_UFS_PHY_ICE_CORE_CLK 153
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 154
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 155
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#define GCC_UFS_PHY_PHY_AUX_CLK 156
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 157
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 158
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 159
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 160
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 161
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 162
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 163
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 164
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#define GCC_USB30_PRIM_MASTER_CLK 165
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 166
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 167
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 168
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 169
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#define GCC_USB30_PRIM_SLEEP_CLK 170
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#define GCC_USB30_SEC_MASTER_CLK 171
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#define GCC_USB30_SEC_MASTER_CLK_SRC 172
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 173
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 174
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 175
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#define GCC_USB30_SEC_SLEEP_CLK 176
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#define GCC_USB3_PRIM_PHY_AUX_CLK 177
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 178
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 179
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 180
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 181
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#define GCC_USB3_SEC_CLKREF_EN 182
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#define GCC_USB3_SEC_PHY_AUX_CLK 183
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 184
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 185
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#define GCC_USB3_SEC_PHY_PIPE_CLK 186
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 187
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#define GCC_VIDEO_AHB_CLK 188
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#define GCC_VIDEO_AXI0_CLK 189
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#define GCC_VIDEO_AXI1_CLK 190
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#define GCC_VIDEO_XO_CLK 191
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#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 192
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#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 193
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
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#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
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#define GCC_BOOT_ROM_AHB_CLK 7
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#define GCC_CAMERA_AHB_CLK 8
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#define GCC_CAMERA_HF_AXI_CLK 9
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#define GCC_CAMERA_SF_AXI_CLK 10
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#define GCC_CAMERA_XO_CLK 11
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
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#define GCC_CPUSS_AHB_CLK 14
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#define GCC_CPUSS_AHB_CLK_SRC 15
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 16
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#define GCC_DDRSS_GPU_AXI_CLK 17
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#define GCC_DDRSS_PCIE_SF_TBU_CLK 18
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#define GCC_DISP_AHB_CLK 19
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#define GCC_DISP_HF_AXI_CLK 20
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#define GCC_DISP_SF_AXI_CLK 21
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#define GCC_DISP_XO_CLK 22
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#define GCC_GP1_CLK 23
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#define GCC_GP1_CLK_SRC 24
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#define GCC_GP2_CLK 25
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#define GCC_GP2_CLK_SRC 26
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#define GCC_GP3_CLK 27
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#define GCC_GP3_CLK_SRC 28
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#define GCC_GPLL0 29
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#define GCC_GPLL0_OUT_EVEN 30
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#define GCC_GPLL4 31
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#define GCC_GPLL9 32
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#define GCC_GPU_CFG_AHB_CLK 33
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#define GCC_GPU_GPLL0_CLK_SRC 34
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
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#define GCC_GPU_IREF_EN 36
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#define GCC_GPU_MEMNOC_GFX_CLK 37
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#define GCC_GPU_SNOC_DVM_GFX_CLK 38
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#define GCC_PCIE0_PHY_RCHNG_CLK 39
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#define GCC_PCIE1_PHY_RCHNG_CLK 40
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#define GCC_PCIE_0_AUX_CLK 41
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#define GCC_PCIE_0_AUX_CLK_SRC 42
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||||
#define GCC_PCIE_0_CFG_AHB_CLK 43
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||||
#define GCC_PCIE_0_CLKREF_EN 44
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||||
#define GCC_PCIE_0_MSTR_AXI_CLK 45
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 46
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||||
#define GCC_PCIE_0_PIPE_CLK 47
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||||
#define GCC_PCIE_0_SLV_AXI_CLK 48
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
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#define GCC_PCIE_1_AUX_CLK 50
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#define GCC_PCIE_1_AUX_CLK_SRC 51
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#define GCC_PCIE_1_CFG_AHB_CLK 52
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||||
#define GCC_PCIE_1_CLKREF_EN 53
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||||
#define GCC_PCIE_1_MSTR_AXI_CLK 54
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 55
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||||
#define GCC_PCIE_1_PIPE_CLK 56
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||||
#define GCC_PCIE_1_SLV_AXI_CLK 57
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||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58
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||||
#define GCC_PDM2_CLK 59
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||||
#define GCC_PDM2_CLK_SRC 60
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||||
#define GCC_PDM_AHB_CLK 61
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||||
#define GCC_PDM_XO4_CLK 62
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||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 63
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||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 64
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||||
#define GCC_QMIP_DISP_AHB_CLK 65
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||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 66
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||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67
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||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68
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||||
#define GCC_QUPV3_WRAP0_CORE_CLK 69
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||||
#define GCC_QUPV3_WRAP0_S0_CLK 70
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||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71
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||||
#define GCC_QUPV3_WRAP0_S1_CLK 72
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||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73
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||||
#define GCC_QUPV3_WRAP0_S2_CLK 74
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||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75
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||||
#define GCC_QUPV3_WRAP0_S3_CLK 76
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||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77
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||||
#define GCC_QUPV3_WRAP0_S4_CLK 78
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||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79
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||||
#define GCC_QUPV3_WRAP0_S5_CLK 80
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||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 81
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||||
#define GCC_QUPV3_WRAP0_S6_CLK 82
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||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 83
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||||
#define GCC_QUPV3_WRAP0_S7_CLK 84
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||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 85
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||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 86
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 87
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||||
#define GCC_QUPV3_WRAP1_S0_CLK 88
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||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 90
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 92
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 94
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 96
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 98
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 100
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 101
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 102
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 103
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 104
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 105
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 106
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 107
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 108
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 109
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 110
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 111
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 112
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 113
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 114
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 115
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 116
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 117
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 118
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 119
|
||||
#define GCC_SDCC2_AHB_CLK 120
|
||||
#define GCC_SDCC2_APPS_CLK 121
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 122
|
||||
#define GCC_SDCC4_AHB_CLK 123
|
||||
#define GCC_SDCC4_APPS_CLK 124
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 125
|
||||
#define GCC_SYS_NOC_CPUSS_AHB_CLK 126
|
||||
#define GCC_UFS_1_CLKREF_EN 127
|
||||
#define GCC_UFS_CARD_AHB_CLK 128
|
||||
#define GCC_UFS_CARD_AXI_CLK 129
|
||||
#define GCC_UFS_CARD_AXI_CLK_SRC 130
|
||||
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 131
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK 132
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 133
|
||||
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 134
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK 135
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 136
|
||||
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 137
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 138
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 139
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 140
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 141
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 142
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 143
|
||||
#define GCC_UFS_PHY_AHB_CLK 144
|
||||
#define GCC_UFS_PHY_AXI_CLK 145
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 146
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 147
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 148
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 149
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 150
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 151
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 152
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 153
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 154
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 155
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 156
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 157
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 158
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 159
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 160
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 161
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 162
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 163
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 164
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 165
|
||||
#define GCC_USB30_SEC_MASTER_CLK 166
|
||||
#define GCC_USB30_SEC_MASTER_CLK_SRC 167
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK 168
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 169
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 170
|
||||
#define GCC_USB30_SEC_SLEEP_CLK 171
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 172
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 173
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 174
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 175
|
||||
#define GCC_USB3_SEC_CLKREF_EN 176
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK 177
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 178
|
||||
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 179
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK 180
|
||||
#define GCC_VIDEO_AHB_CLK 181
|
||||
#define GCC_VIDEO_AXI0_CLK 182
|
||||
#define GCC_VIDEO_AXI1_CLK 183
|
||||
#define GCC_VIDEO_XO_CLK 184
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
#define GCC_DISPLAY_BCR 1
|
||||
#define GCC_DPM_BCR 2
|
||||
#define GCC_GPU_BCR 3
|
||||
#define GCC_MMSS_BCR 4
|
||||
#define GCC_PCIE_0_BCR 5
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 6
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 7
|
||||
#define GCC_PCIE_0_PHY_BCR 8
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 9
|
||||
#define GCC_PCIE_1_BCR 10
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 11
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 12
|
||||
#define GCC_PCIE_1_PHY_BCR 13
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 14
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 15
|
||||
#define GCC_PCIE_PHY_COM_BCR 16
|
||||
#define GCC_PDM_BCR 17
|
||||
#define GCC_QUPV3_WRAPPER_0_BCR 18
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 19
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 20
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 21
|
||||
#define GCC_QUSB2PHY_SEC_BCR 22
|
||||
#define GCC_SDCC2_BCR 23
|
||||
#define GCC_SDCC4_BCR 24
|
||||
#define GCC_UFS_CARD_BCR 25
|
||||
#define GCC_UFS_PHY_BCR 26
|
||||
#define GCC_USB30_PRIM_BCR 27
|
||||
#define GCC_USB30_SEC_BCR 28
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 29
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 30
|
||||
#define GCC_USB3_PHY_PRIM_BCR 31
|
||||
#define GCC_USB3_PHY_SEC_BCR 32
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 33
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 34
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 35
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 36
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 37
|
||||
#define GCC_VIDEO_BCR 38
|
||||
#define GCC_GPU_BCR 2
|
||||
#define GCC_MMSS_BCR 3
|
||||
#define GCC_PCIE_0_BCR 4
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 5
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_BCR 7
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
|
||||
#define GCC_PCIE_1_BCR 9
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 10
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
|
||||
#define GCC_PCIE_1_PHY_BCR 12
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 14
|
||||
#define GCC_PCIE_PHY_COM_BCR 15
|
||||
#define GCC_PDM_BCR 16
|
||||
#define GCC_QUPV3_WRAPPER_0_BCR 17
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 18
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 19
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 20
|
||||
#define GCC_QUSB2PHY_SEC_BCR 21
|
||||
#define GCC_SDCC2_BCR 22
|
||||
#define GCC_SDCC4_BCR 23
|
||||
#define GCC_UFS_CARD_BCR 24
|
||||
#define GCC_UFS_PHY_BCR 25
|
||||
#define GCC_USB30_PRIM_BCR 26
|
||||
#define GCC_USB30_SEC_BCR 27
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 28
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 29
|
||||
#define GCC_USB3_PHY_PRIM_BCR 30
|
||||
#define GCC_USB3_PHY_SEC_BCR 31
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 32
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 33
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 34
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 35
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 36
|
||||
#define GCC_VIDEO_BCR 37
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue