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interconnect: qcom: Add Lahaina interconnect provider driver
Introduce Qualcomm Lahaina specific provider driver using the interconnect framework. Change-Id: Ib9b4423ee1896679d1456c7119befdee55684ad2 Signed-off-by: David Dai <daidavid1@codeaurora.org>
This commit is contained in:
David Dai
parent
1aa77b0e48
commit
81e8ab13ba
3 changed files with 943 additions and 1 deletions
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config INTERCONNECT_QCOM
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bool "Qualcomm Network-on-Chip interconnect drivers"
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tristate "Qualcomm Technologies, Inc. Network-on-Chip interconnect drivers"
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depends on ARCH_QCOM
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help
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Support for Qualcomm's Network-on-Chip interconnect hardware.
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@ -12,3 +12,10 @@ config INTERCONNECT_QCOM_SDM845
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help
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This is a driver for the Qualcomm Network-on-Chip on sdm845-based
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platforms.
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config INTERCONNECT_QCOM_LAHAINA
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tristate "LAHAINA interconnect driver"
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depends on INTERCONNECT_QCOM
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help
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This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip
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on lahaina-based platforms.
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@ -1,5 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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qnoc-sdm845-objs := sdm845.o
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qnoc-lahaina-objs := lahaina.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
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obj-$(CONFIG_INTERCONNECT_QCOM_LAHAINA) += qnoc-lahaina.o
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933
drivers/interconnect/qcom/lahaina.c
Normal file
933
drivers/interconnect/qcom/lahaina.c
Normal file
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@ -0,0 +1,933 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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*/
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#include <asm/div64.h>
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#include <dt-bindings/interconnect/qcom,lahaina.h>
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#include <linux/device.h>
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#include <linux/interconnect.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/sort.h>
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#include <soc/qcom/cmd-db.h>
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#include <soc/qcom/rpmh.h>
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#include <soc/qcom/tcs.h>
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#define to_qcom_provider(_provider) \
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container_of(_provider, struct qcom_icc_provider, provider)
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struct qcom_icc_provider {
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struct icc_provider provider;
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struct device *dev;
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struct qcom_icc_bcm **bcms;
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size_t num_bcms;
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};
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/**
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* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM)
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* @unit: divisor used to convert bytes/sec bw value to an RPMh msg
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* @width: multiplier used to convert bytes/sec bw value to an RPMh msg
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* @vcd: virtual clock domain that this bcm belongs to
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* @reserved: reserved field
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*/
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struct bcm_db {
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__le32 unit;
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__le16 width;
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u8 vcd;
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u8 reserved;
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};
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#define LAHAINA_MAX_LINKS 56
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#define LAHAINA_MAX_BCM_PER_NODE 2
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#define LAHAINA_MAX_VCD 10
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/**
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* struct qcom_icc_node - qcom specific interconnect nodes
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* @name: the node name used in debugfs
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* @links: an array of nodes where we can go next while traversing
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* @id: a unique node identifier
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* @num_links: the total number of @links
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* @channels: num of channels at this node
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* @buswidth: width of the interconnect between a node and the bus
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* @sum_avg: current sum aggregate value of all avg bw requests
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* @max_peak: current max aggregate value of all peak bw requests
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* @bcms: list of bcms associated with this logical node
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* @num_bcms: num of @bcms
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*/
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struct qcom_icc_node {
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const char *name;
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u16 links[LAHAINA_MAX_LINKS];
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u16 id;
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u16 num_links;
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u16 channels;
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u16 buswidth;
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u64 sum_avg;
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u64 max_peak;
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struct qcom_icc_bcm *bcms[LAHAINA_MAX_BCM_PER_NODE];
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size_t num_bcms;
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};
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/**
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* struct qcom_icc_bcm - qcom specific hardware accelerator nodes
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* known as Bus Clock Manager (BCM)
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* @name: the bcm node name used to fetch BCM data from command db
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* @type: latency or bandwidth bcm
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* @addr: address offsets used when voting to RPMH
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* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
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* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
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* @dirty: flag used to indicate whether the bcm needs to be committed
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* @keepalive: flag used to indicate whether a keepalive is required
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* @aux_data: auxiliary data used when calculating threshold values and
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* communicating with RPMh
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* @list: used to link to other bcms when compiling lists for commit
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* @num_nodes: total number of @num_nodes
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* @nodes: list of qcom_icc_nodes that this BCM encapsulates
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*/
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struct qcom_icc_bcm {
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const char *name;
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u32 type;
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u32 addr;
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u64 vote_x;
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u64 vote_y;
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bool dirty;
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bool keepalive;
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struct bcm_db aux_data;
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struct list_head list;
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size_t num_nodes;
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struct qcom_icc_node *nodes[];
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};
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struct qcom_icc_fabric {
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struct qcom_icc_node **nodes;
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size_t num_nodes;
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};
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struct qcom_icc_desc {
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struct qcom_icc_node **nodes;
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size_t num_nodes;
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struct qcom_icc_bcm **bcms;
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size_t num_bcms;
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};
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#define DEFINE_QNODE(_name, _id, _channels, _buswidth, \
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_numlinks, ...) \
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static struct qcom_icc_node _name = { \
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.id = _id, \
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.name = #_name, \
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.channels = _channels, \
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.buswidth = _buswidth, \
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.num_links = _numlinks, \
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.links = { __VA_ARGS__ }, \
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}
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DEFINE_QNODE(qhm_qspi, MASTER_QSPI_0, 1, 4, 1,
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SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(qhm_qup1, MASTER_QUP_1, 1, 4, 1,
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SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(qnm_a1noc_cfg, MASTER_A1NOC_CFG, 1, 4, 1,
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SLAVE_SERVICE_A1NOC);
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DEFINE_QNODE(xm_sdc4, MASTER_SDCC_4, 1, 8, 1,
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SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(xm_ufs_mem, MASTER_UFS_MEM, 1, 8, 1,
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SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(xm_usb3_0, MASTER_USB3_0, 1, 8, 1,
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SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(xm_usb3_1, MASTER_USB3_1, 1, 8, 1,
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SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(qhm_qdss_bam, MASTER_QDSS_BAM, 1, 4, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qhm_qup0, MASTER_QUP_0, 1, 4, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qhm_qup2, MASTER_QUP_2, 1, 4, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qnm_a2noc_cfg, MASTER_A2NOC_CFG, 1, 4, 1,
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SLAVE_SERVICE_A2NOC);
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DEFINE_QNODE(qxm_crypto, MASTER_CRYPTO, 1, 8, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qxm_ipa, MASTER_IPA, 1, 8, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(xm_pcie3_0, MASTER_PCIE_0, 1, 8, 1,
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SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_pcie3_1, MASTER_PCIE_1, 1, 8, 1,
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SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_qdss_etr, MASTER_QDSS_ETR, 1, 8, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(xm_sdc2, MASTER_SDCC_2, 1, 8, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(xm_ufs_card, MASTER_UFS_CARD, 1, 8, 1,
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SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qnm_gemnoc_cnoc, MASTER_GEM_NOC_CNOC, 1, 16, 56,
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SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH,
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SLAVE_AOSS, SLAVE_APPSS,
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SLAVE_CAMERA_CFG, SLAVE_CLK_CTL,
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SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG,
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SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MX_CFG,
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SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM,
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SLAVE_DCC_CFG, SLAVE_DISPLAY_CFG,
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SLAVE_GFX3D_CFG, SLAVE_HWKM,
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SLAVE_IMEM_CFG, SLAVE_IPA_CFG,
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SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS,
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SLAVE_CNOC_MSS, SLAVE_MX_RDPM,
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SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG,
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SLAVE_PDM, SLAVE_PIMEM_CFG,
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SLAVE_PKA_WRAPPER_CFG, SLAVE_PMU_WRAPPER_CFG,
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SLAVE_QDSS_CFG, SLAVE_QSPI_0,
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SLAVE_QUP_0, SLAVE_QUP_1,
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SLAVE_QUP_2, SLAVE_SDCC_2,
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SLAVE_SDCC_4, SLAVE_SECURITY,
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SLAVE_SPSS_CFG, SLAVE_TCSR,
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SLAVE_TLMM, SLAVE_UFS_CARD_CFG,
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SLAVE_UFS_MEM_CFG, SLAVE_USB3_0,
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SLAVE_USB3_1, SLAVE_VENUS_CFG,
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SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG,
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SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG,
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SLAVE_CNOC_MNOC_CFG, SLAVE_SNOC_CFG,
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SLAVE_BOOT_IMEM, SLAVE_IMEM,
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SLAVE_PIMEM, SLAVE_SERVICE_CNOC,
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SLAVE_QDSS_STM, SLAVE_TCU);
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DEFINE_QNODE(qnm_gemnoc_pcie, MASTER_GEM_NOC_PCIE_SNOC, 1, 8, 2,
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SLAVE_PCIE_0, SLAVE_PCIE_1);
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DEFINE_QNODE(xm_qdss_dap, MASTER_QDSS_DAP, 1, 8, 56,
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SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH,
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SLAVE_AOSS, SLAVE_APPSS,
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SLAVE_CAMERA_CFG, SLAVE_CLK_CTL,
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SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG,
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SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MX_CFG,
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SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM,
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SLAVE_DCC_CFG, SLAVE_DISPLAY_CFG,
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SLAVE_GFX3D_CFG, SLAVE_HWKM,
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SLAVE_IMEM_CFG, SLAVE_IPA_CFG,
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SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS,
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SLAVE_CNOC_MSS, SLAVE_MX_RDPM,
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SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG,
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SLAVE_PDM, SLAVE_PIMEM_CFG,
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SLAVE_PKA_WRAPPER_CFG, SLAVE_PMU_WRAPPER_CFG,
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SLAVE_QDSS_CFG, SLAVE_QSPI_0,
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SLAVE_QUP_0, SLAVE_QUP_1,
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SLAVE_QUP_2, SLAVE_SDCC_2,
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SLAVE_SDCC_4, SLAVE_SECURITY,
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SLAVE_SPSS_CFG, SLAVE_TCSR,
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SLAVE_TLMM, SLAVE_UFS_CARD_CFG,
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SLAVE_UFS_MEM_CFG, SLAVE_USB3_0,
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SLAVE_USB3_1, SLAVE_VENUS_CFG,
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SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG,
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SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG,
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SLAVE_CNOC_MNOC_CFG, SLAVE_SNOC_CFG,
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SLAVE_BOOT_IMEM, SLAVE_IMEM,
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SLAVE_PIMEM, SLAVE_SERVICE_CNOC,
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SLAVE_QDSS_STM, SLAVE_TCU);
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DEFINE_QNODE(qnm_cnoc_dc_noc, MASTER_CNOC_DC_NOC, 1, 4, 2,
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SLAVE_LLCC_CFG, SLAVE_GEM_NOC_CFG);
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DEFINE_QNODE(alm_gpu_tcu, MASTER_GPU_TCU, 1, 8, 2,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC);
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DEFINE_QNODE(alm_sys_tcu, MASTER_SYS_TCU, 1, 8, 2,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC);
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DEFINE_QNODE(chm_apps, MASTER_APPSS_PROC, 2, 32, 3,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_MEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(qnm_cmpnoc, MASTER_COMPUTE_NOC, 2, 32, 2,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC);
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DEFINE_QNODE(qnm_gemnoc_cfg, MASTER_GEM_NOC_CFG, 1, 4, 5,
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SLAVE_MSS_PROC_MS_MPU_CFG, SLAVE_MCDMA_MS_MPU_CFG,
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SLAVE_SERVICE_GEM_NOC_1, SLAVE_SERVICE_GEM_NOC_2,
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SLAVE_SERVICE_GEM_NOC);
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DEFINE_QNODE(qnm_gpu, MASTER_GFX3D, 2, 32, 2,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC);
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DEFINE_QNODE(qnm_mnoc_hf, MASTER_MNOC_HF_MEM_NOC, 2, 32, 1,
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SLAVE_LLCC);
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DEFINE_QNODE(qnm_mnoc_sf, MASTER_MNOC_SF_MEM_NOC, 2, 32, 2,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC);
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DEFINE_QNODE(qnm_pcie, MASTER_ANOC_PCIE_GEM_NOC, 1, 16, 2,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC);
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DEFINE_QNODE(qnm_snoc_gc, MASTER_SNOC_GC_MEM_NOC, 1, 8, 1,
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SLAVE_LLCC);
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DEFINE_QNODE(qnm_snoc_sf, MASTER_SNOC_SF_MEM_NOC, 1, 16, 3,
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SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_MEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(qhm_config_noc, MASTER_CNOC_LPASS_AG_NOC, 1, 4, 6,
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SLAVE_LPASS_CORE_CFG, SLAVE_LPASS_LPI_CFG,
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SLAVE_LPASS_MPU_CFG, SLAVE_LPASS_TOP_CFG,
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SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC);
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DEFINE_QNODE(llcc_mc, MASTER_LLCC, 4, 4, 1,
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SLAVE_EBI1);
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DEFINE_QNODE(qnm_camnoc_hf, MASTER_CAMNOC_HF, 2, 32, 1,
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SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qnm_camnoc_icp, MASTER_CAMNOC_ICP, 1, 8, 1,
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SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_camnoc_sf, MASTER_CAMNOC_SF, 2, 32, 1,
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SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_mnoc_cfg, MASTER_CNOC_MNOC_CFG, 1, 4, 1,
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SLAVE_SERVICE_MNOC);
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DEFINE_QNODE(qnm_video0, MASTER_VIDEO_P0, 1, 32, 1,
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SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video1, MASTER_VIDEO_P1, 1, 32, 1,
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SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video_cvp, MASTER_VIDEO_PROC, 1, 32, 1,
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SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp0, MASTER_MDP0, 1, 32, 1,
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SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp1, MASTER_MDP1, 1, 32, 1,
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SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_rot, MASTER_ROTATOR, 1, 32, 1,
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SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qhm_nsp_noc_config, MASTER_CDSP_NOC_CFG, 1, 4, 1,
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SLAVE_SERVICE_NSP_NOC);
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DEFINE_QNODE(qxm_nsp, MASTER_CDSP_PROC, 2, 32, 1,
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SLAVE_CDSP_MEM_NOC);
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DEFINE_QNODE(qnm_aggre1_noc, MASTER_A1NOC_SNOC, 1, 16, 1,
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SLAVE_SNOC_GEM_NOC_SF);
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DEFINE_QNODE(qnm_aggre2_noc, MASTER_A2NOC_SNOC, 1, 16, 1,
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SLAVE_SNOC_GEM_NOC_SF);
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DEFINE_QNODE(qnm_snoc_cfg, MASTER_SNOC_CFG, 1, 4, 1,
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SLAVE_SERVICE_SNOC);
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DEFINE_QNODE(qxm_pimem, MASTER_PIMEM, 1, 8, 1,
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SLAVE_SNOC_GEM_NOC_GC);
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DEFINE_QNODE(xm_gic, MASTER_GIC, 1, 8, 1,
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SLAVE_SNOC_GEM_NOC_GC);
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DEFINE_QNODE(qns_a1noc_snoc, SLAVE_A1NOC_SNOC, 1, 16, 1,
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MASTER_A1NOC_SNOC);
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DEFINE_QNODE(srvc_aggre1_noc, SLAVE_SERVICE_A1NOC, 1, 4, 0);
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DEFINE_QNODE(qns_a2noc_snoc, SLAVE_A2NOC_SNOC, 1, 16, 1,
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MASTER_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qns_pcie_mem_noc, SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, 1,
|
||||
MASTER_ANOC_PCIE_GEM_NOC);
|
||||
DEFINE_QNODE(srvc_aggre2_noc, SLAVE_SERVICE_A2NOC, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_ahb2phy0, SLAVE_AHB2PHY_SOUTH, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_ahb2phy1, SLAVE_AHB2PHY_NORTH, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_aoss, SLAVE_AOSS, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_apss, SLAVE_APPSS, 1, 8, 0);
|
||||
DEFINE_QNODE(qhs_camera_cfg, SLAVE_CAMERA_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_clk_ctl, SLAVE_CLK_CTL, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_compute_cfg, SLAVE_CDSP_CFG, 1, 4, 1,
|
||||
MASTER_CDSP_NOC_CFG);
|
||||
DEFINE_QNODE(qhs_cpr_cx, SLAVE_RBCPR_CX_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_cpr_mmcx, SLAVE_RBCPR_MMCX_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_cpr_mx, SLAVE_RBCPR_MX_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_crypto0_cfg, SLAVE_CRYPTO_0_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_cx_rdpm, SLAVE_CX_RDPM, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_dcc_cfg, SLAVE_DCC_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_display_cfg, SLAVE_DISPLAY_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_gpuss_cfg, SLAVE_GFX3D_CFG, 1, 8, 0);
|
||||
DEFINE_QNODE(qhs_hwkm, SLAVE_HWKM, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_imem_cfg, SLAVE_IMEM_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_ipa, SLAVE_IPA_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_ipc_router, SLAVE_IPC_ROUTER_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_lpass_cfg, SLAVE_LPASS, 1, 4, 1,
|
||||
MASTER_CNOC_LPASS_AG_NOC);
|
||||
DEFINE_QNODE(qhs_mss_cfg, SLAVE_CNOC_MSS, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_mx_rdpm, SLAVE_MX_RDPM, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_pcie0_cfg, SLAVE_PCIE_0_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_pcie1_cfg, SLAVE_PCIE_1_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_pdm, SLAVE_PDM, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_pimem_cfg, SLAVE_PIMEM_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_pka_wrapper_cfg, SLAVE_PKA_WRAPPER_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_pmu_wrapper_cfg, SLAVE_PMU_WRAPPER_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_qdss_cfg, SLAVE_QDSS_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_qspi, SLAVE_QSPI_0, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_qup0, SLAVE_QUP_0, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_qup1, SLAVE_QUP_1, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_qup2, SLAVE_QUP_2, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_sdc2, SLAVE_SDCC_2, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_sdc4, SLAVE_SDCC_4, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_security, SLAVE_SECURITY, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_spss_cfg, SLAVE_SPSS_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_tcsr, SLAVE_TCSR, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_tlmm, SLAVE_TLMM, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_ufs_card_cfg, SLAVE_UFS_CARD_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_ufs_mem_cfg, SLAVE_UFS_MEM_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_usb3_0, SLAVE_USB3_0, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_usb3_1, SLAVE_USB3_1, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_venus_cfg, SLAVE_VENUS_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SLAVE_VSENSE_CTRL_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qns_a1_noc_cfg, SLAVE_A1NOC_CFG, 1, 4, 1,
|
||||
MASTER_A1NOC_CFG);
|
||||
DEFINE_QNODE(qns_a2_noc_cfg, SLAVE_A2NOC_CFG, 1, 4, 1,
|
||||
MASTER_A2NOC_CFG);
|
||||
DEFINE_QNODE(qns_ddrss_cfg, SLAVE_DDRSS_CFG, 1, 4, 1,
|
||||
MASTER_CNOC_DC_NOC);
|
||||
DEFINE_QNODE(qns_mnoc_cfg, SLAVE_CNOC_MNOC_CFG, 1, 4, 1,
|
||||
MASTER_CNOC_MNOC_CFG);
|
||||
DEFINE_QNODE(qns_snoc_cfg, SLAVE_SNOC_CFG, 1, 4, 1,
|
||||
MASTER_SNOC_CFG);
|
||||
DEFINE_QNODE(qxs_boot_imem, SLAVE_BOOT_IMEM, 1, 8, 0);
|
||||
DEFINE_QNODE(qxs_imem, SLAVE_IMEM, 1, 8, 0);
|
||||
DEFINE_QNODE(qxs_pimem, SLAVE_PIMEM, 1, 8, 0);
|
||||
DEFINE_QNODE(srvc_cnoc, SLAVE_SERVICE_CNOC, 1, 4, 0);
|
||||
DEFINE_QNODE(xs_pcie_0, SLAVE_PCIE_0, 1, 8, 0);
|
||||
DEFINE_QNODE(xs_pcie_1, SLAVE_PCIE_1, 1, 8, 0);
|
||||
DEFINE_QNODE(xs_qdss_stm, SLAVE_QDSS_STM, 1, 4, 0);
|
||||
DEFINE_QNODE(xs_sys_tcu_cfg, SLAVE_TCU, 1, 8, 0);
|
||||
DEFINE_QNODE(qhs_llcc, SLAVE_LLCC_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qns_gemnoc, SLAVE_GEM_NOC_CFG, 1, 4, 1,
|
||||
MASTER_GEM_NOC_CFG);
|
||||
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SLAVE_MCDMA_MS_MPU_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qns_gem_noc_cnoc, SLAVE_GEM_NOC_CNOC, 1, 16, 1,
|
||||
MASTER_GEM_NOC_CNOC);
|
||||
DEFINE_QNODE(qns_llcc, SLAVE_LLCC, 4, 16, 1,
|
||||
MASTER_LLCC);
|
||||
DEFINE_QNODE(qns_pcie, SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, 1,
|
||||
MASTER_GEM_NOC_PCIE_SNOC);
|
||||
DEFINE_QNODE(srvc_even_gemnoc, SLAVE_SERVICE_GEM_NOC_1, 1, 4, 0);
|
||||
DEFINE_QNODE(srvc_odd_gemnoc, SLAVE_SERVICE_GEM_NOC_2, 1, 4, 0);
|
||||
DEFINE_QNODE(srvc_sys_gemnoc, SLAVE_SERVICE_GEM_NOC, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_lpass_core, SLAVE_LPASS_CORE_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_lpass_lpi, SLAVE_LPASS_LPI_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_lpass_mpu, SLAVE_LPASS_MPU_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(qhs_lpass_top, SLAVE_LPASS_TOP_CFG, 1, 4, 0);
|
||||
DEFINE_QNODE(srvc_niu_aml_noc, SLAVE_SERVICES_LPASS_AML_NOC, 1, 4, 0);
|
||||
DEFINE_QNODE(srvc_niu_lpass_agnoc, SLAVE_SERVICE_LPASS_AG_NOC, 1, 4, 0);
|
||||
DEFINE_QNODE(ebi, SLAVE_EBI1, 4, 4, 0);
|
||||
DEFINE_QNODE(qns_mem_noc_hf, SLAVE_MNOC_HF_MEM_NOC, 2, 32, 1,
|
||||
MASTER_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qns_mem_noc_sf, SLAVE_MNOC_SF_MEM_NOC, 2, 32, 1,
|
||||
MASTER_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(srvc_mnoc, SLAVE_SERVICE_MNOC, 1, 4, 0);
|
||||
DEFINE_QNODE(qns_nsp_gemnoc, SLAVE_CDSP_MEM_NOC, 2, 32, 1,
|
||||
MASTER_COMPUTE_NOC);
|
||||
DEFINE_QNODE(service_nsp_noc, SLAVE_SERVICE_NSP_NOC, 1, 4, 0);
|
||||
DEFINE_QNODE(qns_gemnoc_gc, SLAVE_SNOC_GEM_NOC_GC, 1, 8, 1,
|
||||
MASTER_SNOC_GC_MEM_NOC);
|
||||
DEFINE_QNODE(qns_gemnoc_sf, SLAVE_SNOC_GEM_NOC_SF, 1, 16, 1,
|
||||
MASTER_SNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(srvc_snoc, SLAVE_SERVICE_SNOC, 1, 4, 0);
|
||||
|
||||
|
||||
#define DEFINE_QBCM(_name, _bcmname, _keepalive, _numnodes, ...) \
|
||||
static struct qcom_icc_bcm _name = { \
|
||||
.name = _bcmname, \
|
||||
.keepalive = _keepalive, \
|
||||
.num_nodes = _numnodes, \
|
||||
.nodes = { __VA_ARGS__ }, \
|
||||
}
|
||||
|
||||
DEFINE_QBCM(bcm_acv, "ACV", 1, false,
|
||||
&ebi);
|
||||
DEFINE_QBCM(bcm_mc0, "MC0", 1, false,
|
||||
&ebi);
|
||||
DEFINE_QBCM(bcm_sh0, "SH0", 1, false,
|
||||
&qns_llcc);
|
||||
DEFINE_QBCM(bcm_mm0, "MM0", 1, false,
|
||||
&qns_mem_noc_hf);
|
||||
DEFINE_QBCM(bcm_co0, "CO0", 1, false,
|
||||
&qns_nsp_gemnoc);
|
||||
DEFINE_QBCM(bcm_ce0, "CE0", 1, false,
|
||||
&qxm_crypto);
|
||||
DEFINE_QBCM(bcm_cn0, "CN0", 47, false,
|
||||
&xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1,
|
||||
&qhs_aoss, &qhs_apss, &qhs_camera_cfg,
|
||||
&qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx,
|
||||
&qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg,
|
||||
&qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg,
|
||||
&qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg,
|
||||
&qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg,
|
||||
&qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg,
|
||||
&qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg,
|
||||
&qhs_qdss_cfg, &qhs_qup0, &qhs_qup1,
|
||||
&qhs_qup2, &qhs_security, &qhs_spss_cfg,
|
||||
&qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg,
|
||||
&qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1,
|
||||
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg,
|
||||
&qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg,
|
||||
&qns_snoc_cfg, &srvc_cnoc);
|
||||
DEFINE_QBCM(bcm_mm1, "MM1", 3, false,
|
||||
&qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
|
||||
DEFINE_QBCM(bcm_cn1, "CN1", 5, false,
|
||||
&qhs_lpass_cfg, &qhs_pdm, &qhs_qspi,
|
||||
&qhs_sdc2, &qhs_sdc4);
|
||||
DEFINE_QBCM(bcm_sh2, "SH2", 2, false,
|
||||
&alm_gpu_tcu, &alm_sys_tcu);
|
||||
DEFINE_QBCM(bcm_cn2, "CN2", 2, false,
|
||||
&qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
|
||||
DEFINE_QBCM(bcm_co3, "CO3", 1, false,
|
||||
&qxm_nsp);
|
||||
DEFINE_QBCM(bcm_qup0, "QUP0", 1, false,
|
||||
&qhm_qup0);
|
||||
DEFINE_QBCM(bcm_qup1, "QUP1", 1, false,
|
||||
&qhm_qup1);
|
||||
DEFINE_QBCM(bcm_sh3, "SH3", 1, false,
|
||||
&qnm_cmpnoc);
|
||||
DEFINE_QBCM(bcm_sh4, "SH4", 1, false,
|
||||
&chm_apps);
|
||||
DEFINE_QBCM(bcm_mm4, "MM4", 1, false,
|
||||
&qns_mem_noc_sf);
|
||||
DEFINE_QBCM(bcm_mm5, "MM5", 6, false,
|
||||
&qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0,
|
||||
&qnm_video1, &qnm_video_cvp, &qxm_rot);
|
||||
DEFINE_QBCM(bcm_qup2, "QUP2", 1, false,
|
||||
&qhm_qup2);
|
||||
DEFINE_QBCM(bcm_sn0, "SN0", 1, false,
|
||||
&qns_gemnoc_sf);
|
||||
DEFINE_QBCM(bcm_sn2, "SN2", 1, false,
|
||||
&qns_gemnoc_gc);
|
||||
DEFINE_QBCM(bcm_sn3, "SN3", 1, false,
|
||||
&qxs_pimem);
|
||||
DEFINE_QBCM(bcm_sn4, "SN4", 1, false,
|
||||
&xs_qdss_stm);
|
||||
DEFINE_QBCM(bcm_sn5, "SN5", 1, false,
|
||||
&xm_pcie3_0);
|
||||
DEFINE_QBCM(bcm_sn6, "SN6", 1, false,
|
||||
&xm_pcie3_1);
|
||||
DEFINE_QBCM(bcm_sn7, "SN7", 1, false,
|
||||
&qnm_aggre1_noc);
|
||||
DEFINE_QBCM(bcm_sn8, "SN8", 1, false,
|
||||
&qnm_aggre2_noc);
|
||||
DEFINE_QBCM(bcm_sn14, "SN14", 1, false,
|
||||
&qns_pcie_mem_noc);
|
||||
|
||||
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
|
||||
&bcm_qup1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre1_noc_nodes[] = {
|
||||
[MASTER_QSPI_0] = &qhm_qspi,
|
||||
[MASTER_QUP_1] = &qhm_qup1,
|
||||
[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
|
||||
[MASTER_SDCC_4] = &xm_sdc4,
|
||||
[MASTER_UFS_MEM] = &xm_ufs_mem,
|
||||
[MASTER_USB3_0] = &xm_usb3_0,
|
||||
[MASTER_USB3_1] = &xm_usb3_1,
|
||||
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
|
||||
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_aggre1_noc = {
|
||||
.nodes = aggre1_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
|
||||
.bcms = aggre1_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
|
||||
&bcm_qup0,
|
||||
&bcm_ce0,
|
||||
&bcm_qup2,
|
||||
&bcm_sn5,
|
||||
&bcm_sn6,
|
||||
&bcm_sn14,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre2_noc_nodes[] = {
|
||||
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
|
||||
[MASTER_QUP_0] = &qhm_qup0,
|
||||
[MASTER_QUP_2] = &qhm_qup2,
|
||||
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
|
||||
[MASTER_CRYPTO] = &qxm_crypto,
|
||||
[MASTER_IPA] = &qxm_ipa,
|
||||
[MASTER_PCIE_0] = &xm_pcie3_0,
|
||||
[MASTER_PCIE_1] = &xm_pcie3_1,
|
||||
[MASTER_QDSS_ETR] = &xm_qdss_etr,
|
||||
[MASTER_SDCC_2] = &xm_sdc2,
|
||||
[MASTER_UFS_CARD] = &xm_ufs_card,
|
||||
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
|
||||
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
|
||||
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_aggre2_noc = {
|
||||
.nodes = aggre2_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
|
||||
.bcms = aggre2_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *config_noc_bcms[] = {
|
||||
&bcm_cn0,
|
||||
&bcm_cn1,
|
||||
&bcm_cn2,
|
||||
&bcm_sn3,
|
||||
&bcm_sn4,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *config_noc_nodes[] = {
|
||||
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
|
||||
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
|
||||
[MASTER_QDSS_DAP] = &xm_qdss_dap,
|
||||
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
|
||||
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
|
||||
[SLAVE_AOSS] = &qhs_aoss,
|
||||
[SLAVE_APPSS] = &qhs_apss,
|
||||
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
|
||||
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
|
||||
[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
|
||||
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
|
||||
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
|
||||
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
|
||||
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
|
||||
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
|
||||
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
|
||||
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
|
||||
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
|
||||
[SLAVE_HWKM] = &qhs_hwkm,
|
||||
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
|
||||
[SLAVE_IPA_CFG] = &qhs_ipa,
|
||||
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
|
||||
[SLAVE_LPASS] = &qhs_lpass_cfg,
|
||||
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
|
||||
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
|
||||
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
|
||||
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
|
||||
[SLAVE_PDM] = &qhs_pdm,
|
||||
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
|
||||
[SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
|
||||
[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
|
||||
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
|
||||
[SLAVE_QSPI_0] = &qhs_qspi,
|
||||
[SLAVE_QUP_0] = &qhs_qup0,
|
||||
[SLAVE_QUP_1] = &qhs_qup1,
|
||||
[SLAVE_QUP_2] = &qhs_qup2,
|
||||
[SLAVE_SDCC_2] = &qhs_sdc2,
|
||||
[SLAVE_SDCC_4] = &qhs_sdc4,
|
||||
[SLAVE_SECURITY] = &qhs_security,
|
||||
[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
|
||||
[SLAVE_TCSR] = &qhs_tcsr,
|
||||
[SLAVE_TLMM] = &qhs_tlmm,
|
||||
[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
|
||||
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
|
||||
[SLAVE_USB3_0] = &qhs_usb3_0,
|
||||
[SLAVE_USB3_1] = &qhs_usb3_1,
|
||||
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
|
||||
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
|
||||
[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
|
||||
[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
|
||||
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
|
||||
[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
|
||||
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
|
||||
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
|
||||
[SLAVE_IMEM] = &qxs_imem,
|
||||
[SLAVE_PIMEM] = &qxs_pimem,
|
||||
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
|
||||
[SLAVE_PCIE_0] = &xs_pcie_0,
|
||||
[SLAVE_PCIE_1] = &xs_pcie_1,
|
||||
[SLAVE_QDSS_STM] = &xs_qdss_stm,
|
||||
[SLAVE_TCU] = &xs_sys_tcu_cfg,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_config_noc = {
|
||||
.nodes = config_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(config_noc_nodes),
|
||||
.bcms = config_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(config_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *dc_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *dc_noc_nodes[] = {
|
||||
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
|
||||
[SLAVE_LLCC_CFG] = &qhs_llcc,
|
||||
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_dc_noc = {
|
||||
.nodes = dc_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
|
||||
.bcms = dc_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *gem_noc_bcms[] = {
|
||||
&bcm_sh0,
|
||||
&bcm_sh2,
|
||||
&bcm_sh3,
|
||||
&bcm_sh4,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *gem_noc_nodes[] = {
|
||||
[MASTER_GPU_TCU] = &alm_gpu_tcu,
|
||||
[MASTER_SYS_TCU] = &alm_sys_tcu,
|
||||
[MASTER_APPSS_PROC] = &chm_apps,
|
||||
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
|
||||
[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
|
||||
[MASTER_GFX3D] = &qnm_gpu,
|
||||
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
|
||||
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
|
||||
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
|
||||
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
|
||||
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
|
||||
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
|
||||
[SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
|
||||
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
|
||||
[SLAVE_LLCC] = &qns_llcc,
|
||||
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
|
||||
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
|
||||
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
|
||||
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_gem_noc = {
|
||||
.nodes = gem_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
||||
.bcms = gem_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
|
||||
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
|
||||
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
|
||||
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
|
||||
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
|
||||
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
|
||||
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
|
||||
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_lpass_ag_noc = {
|
||||
.nodes = lpass_ag_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
|
||||
.bcms = lpass_ag_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *mc_virt_nodes[] = {
|
||||
[MASTER_LLCC] = &llcc_mc,
|
||||
[SLAVE_EBI1] = &ebi,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_mc_virt = {
|
||||
.nodes = mc_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
|
||||
.bcms = mc_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
|
||||
&bcm_mm0,
|
||||
&bcm_mm1,
|
||||
&bcm_mm4,
|
||||
&bcm_mm5,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *mmss_noc_nodes[] = {
|
||||
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
|
||||
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
|
||||
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
|
||||
[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
|
||||
[MASTER_VIDEO_P0] = &qnm_video0,
|
||||
[MASTER_VIDEO_P1] = &qnm_video1,
|
||||
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
|
||||
[MASTER_MDP0] = &qxm_mdp0,
|
||||
[MASTER_MDP1] = &qxm_mdp1,
|
||||
[MASTER_ROTATOR] = &qxm_rot,
|
||||
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
|
||||
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
|
||||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_mmss_noc = {
|
||||
.nodes = mmss_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
|
||||
.bcms = mmss_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *nsp_noc_bcms[] = {
|
||||
&bcm_co0,
|
||||
&bcm_co3,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *nsp_noc_nodes[] = {
|
||||
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
|
||||
[MASTER_CDSP_PROC] = &qxm_nsp,
|
||||
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
|
||||
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_nsp_noc = {
|
||||
.nodes = nsp_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
|
||||
.bcms = nsp_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *system_noc_bcms[] = {
|
||||
&bcm_sn0,
|
||||
&bcm_sn2,
|
||||
&bcm_sn7,
|
||||
&bcm_sn8,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *system_noc_nodes[] = {
|
||||
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
|
||||
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
|
||||
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
|
||||
[MASTER_PIMEM] = &qxm_pimem,
|
||||
[MASTER_GIC] = &xm_gic,
|
||||
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
|
||||
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
|
||||
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc lahaina_system_noc = {
|
||||
.nodes = system_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
||||
.bcms = system_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||
};
|
||||
|
||||
static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qnoc_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_icc_desc *desc;
|
||||
struct icc_onecell_data *data;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node **qnodes;
|
||||
struct qcom_icc_provider *qp;
|
||||
struct icc_node *node;
|
||||
size_t num_nodes, i;
|
||||
int ret;
|
||||
|
||||
desc = of_device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
qnodes = desc->nodes;
|
||||
num_nodes = desc->num_nodes;
|
||||
|
||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
||||
if (!qp)
|
||||
return -ENOMEM;
|
||||
|
||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
provider = &qp->provider;
|
||||
provider->dev = &pdev->dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->aggregate = qcom_icc_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
provider->data = data;
|
||||
|
||||
qp->dev = &pdev->dev;
|
||||
qp->bcms = desc->bcms;
|
||||
qp->num_bcms = desc->num_bcms;
|
||||
|
||||
ret = icc_provider_add(provider);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_nodes; i++) {
|
||||
size_t j;
|
||||
|
||||
if (!qnodes[i])
|
||||
continue;
|
||||
|
||||
node = icc_node_create(qnodes[i]->id);
|
||||
if (IS_ERR(node)) {
|
||||
ret = PTR_ERR(node);
|
||||
goto err;
|
||||
}
|
||||
|
||||
node->name = qnodes[i]->name;
|
||||
node->data = qnodes[i];
|
||||
icc_node_add(node, provider);
|
||||
|
||||
dev_dbg(&pdev->dev, "registered node %pK %s %d\n", node,
|
||||
qnodes[i]->name, node->id);
|
||||
|
||||
/* populate links */
|
||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||
icc_link_create(node, qnodes[i]->links[j]);
|
||||
|
||||
data->nodes[i] = node;
|
||||
}
|
||||
data->num_nodes = num_nodes;
|
||||
|
||||
platform_set_drvdata(pdev, qp);
|
||||
|
||||
dev_dbg(&pdev->dev, "Registered LAHAINA ICC\n");
|
||||
|
||||
return ret;
|
||||
err:
|
||||
list_for_each_entry(node, &provider->nodes, node_list) {
|
||||
icc_node_del(node);
|
||||
icc_node_destroy(node->id);
|
||||
}
|
||||
|
||||
icc_provider_del(provider);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qnoc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
||||
struct icc_provider *provider = &qp->provider;
|
||||
struct icc_node *n;
|
||||
|
||||
list_for_each_entry(n, &provider->nodes, node_list) {
|
||||
icc_node_del(n);
|
||||
icc_node_destroy(n->id);
|
||||
}
|
||||
|
||||
return icc_provider_del(provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id qnoc_of_match[] = {
|
||||
{ .compatible = "qcom,lahaina-aggre1_noc",
|
||||
.data = &lahaina_aggre1_noc},
|
||||
{ .compatible = "qcom,lahaina-aggre2_noc",
|
||||
.data = &lahaina_aggre2_noc},
|
||||
{ .compatible = "qcom,lahaina-config_noc",
|
||||
.data = &lahaina_config_noc},
|
||||
{ .compatible = "qcom,lahaina-dc_noc",
|
||||
.data = &lahaina_dc_noc},
|
||||
{ .compatible = "qcom,lahaina-gem_noc",
|
||||
.data = &lahaina_gem_noc},
|
||||
{ .compatible = "qcom,lahaina-lpass_ag_noc",
|
||||
.data = &lahaina_lpass_ag_noc},
|
||||
{ .compatible = "qcom,lahaina-mc_virt",
|
||||
.data = &lahaina_mc_virt},
|
||||
{ .compatible = "qcom,lahaina-mmss_noc",
|
||||
.data = &lahaina_mmss_noc},
|
||||
{ .compatible = "qcom,lahaina-nsp_noc",
|
||||
.data = &lahaina_nsp_noc},
|
||||
{ .compatible = "qcom,lahaina-system_noc",
|
||||
.data = &lahaina_system_noc},
|
||||
{ .compatible = "qcom,lahaina-gem_noc",
|
||||
.data = &lahaina_gem_noc},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||
|
||||
static struct platform_driver qnoc_driver = {
|
||||
.probe = qnoc_probe,
|
||||
.remove = qnoc_remove,
|
||||
.driver = {
|
||||
.name = "qnoc-lahaina",
|
||||
.of_match_table = qnoc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qnoc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Lahaina NoC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue