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Merge "ipa: Support IPA offload on msmnile_gvmq target"

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This commit is contained in:
qctecmdr 2020-11-02 12:07:34 -08:00 • committed by Gerrit - the friendly Code Review server
commit 82e754aa5b
11 changed files with 392 additions and 19 deletions
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9
config/dataipa_gsi_V1.h Normal file
View file

@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#define CONFIG_GSI 1
#define CONFIG_RMNET_IPA3 1
#define CONFIG_RNDIS_IPA 1
#define CONFIG_IPA_WDI_UNIFIED_API 1

5
config/dataipa_gsi_V1_GKI.conf Normal file
View file

@ -0,0 +1,5 @@
export CONFIG_GSI=m
export CONFIG_IPA_CLIENTS_MANAGER=m
export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=m

5
config/dataipa_gsi_V1_QGKI.conf Normal file
View file

@ -0,0 +1,5 @@
export CONFIG_GSI=y
export CONFIG_IPA_CLIENTS_MANAGER=y
export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=y

13
drivers/platform/msm/Makefile
View file

@ -26,6 +26,19 @@ include $(srctree)/techpack/dataipa/config/dataipa_GKI.conf
endif
endif
ifeq ($(CONFIG_QTI_QUIN_GVM),y)
LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa_gsi_V1.h
ifeq ($(CONFIG_QGKI),y)
include $(srctree)/techpack/dataipa/config/dataipa_gsi_V1_QGKI.conf
ifeq ($(CONFIG_LOCALVERSION), "-qgki-debug")
include $(srctree)/techpack/dataipa/config/dataipa_debug.conf
LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa_debug.h
endif
else
include $(srctree)/techpack/dataipa/config/dataipa_gsi_V1_GKI.conf
endif
endif
DATAIPADRVTOP = $(srctree)/techpack/dataipa/drivers/platform/msm
ifneq (,$(filter $(CONFIG_IPA3),y m))

130
drivers/platform/msm/gsi/gsi_reg_v1.h
View file

@ -442,6 +442,8 @@
#define GSI_V2_2_GSI_INST_RAM_n_MAXn 4095
#define GSI_V2_5_GSI_INST_RAM_n_MAXn 8191
#define GSI_V2_7_GSI_INST_RAM_n_MAXn 5119
#define GSI_V2_9_GSI_INST_RAM_n_MAXn 6143
#define GSI_V2_11_GSI_INST_RAM_n_MAXn 5119
#define GSI_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000
#define GSI_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18
@ -476,6 +478,11 @@
#define GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff
#define GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0000f004 + 0x4000 * (n) + 0x80 * (k))
#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xfffff
#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
#define GSI_EE_n_GSI_CH_k_CNTXT_2_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0001c008 + 0x4000 * (n) + 0x80 * (k))
#define GSI_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff
@ -549,6 +556,20 @@
#define GSI_V2_5_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf
#define GSI_V2_5_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0000f05c + 0x4000 * (n) + 0x80 * (k))
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0
#define GSI_EE_n_GSI_CH_k_SCRATCH_0_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0001c060 + 0x4000 * (n) + 0x80 * (k))
@ -590,6 +611,11 @@
#define GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff
#define GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x00010004 + 0x4000 * (n) + 0x80 * (k))
#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xfffff
#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
#define GSI_EE_n_EV_CH_k_CNTXT_2_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0001d008 + 0x4000 * (n) + 0x80 * (k))
#define GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff
@ -850,6 +876,110 @@
#define GSI_V2_5_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4
#define GSI_V2_5_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_OFFS(n) \
(GSI_GSI_REG_BASE_OFFS + 0x00012040 + 0x4000 * (n))
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x8000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0xf
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x4000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0xE
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_RMSK 0x7fff
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_MAXn 2
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7F80000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(n) \
(GSI_GSI_REG_BASE_OFFS + 0x00012040 + 0x4000 * (n))
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_MAXn 2
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_INI(n) \
in_dword_masked(GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(n), \
GSI_V2_9_EE_n_GSI_HW_PARAM_2_RMSK)
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_INMI(n, mask) \
in_dword_masked(GSI_V2_9_EE_n_GSI_HW_PARAM_2_OFFS(n), \
mask)
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7f80000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
#define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_OFFS(n) \
(GSI_GSI_REG_BASE_OFFS + 0x00012040 + 0x4000 * (n))
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_MAXn 2
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7F80000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4
#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5
#define GSI_GSI_IRAM_PTR_MSI_DB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00000414)
#define GSI_GSI_IRAM_PTR_MSI_DB_FULL_RMSK 0xfff
#define GSI_GSI_IRAM_PTR_MSI_DB_FULL_IRAM_PTR_BMSK 0xfff
#define GSI_GSI_IRAM_PTR_MSI_DB_FULL_IRAM_PTR_SHFT 0x0
#define GSI_EE_n_GSI_SW_VERSION_OFFS(n) \
(GSI_GSI_REG_BASE_OFFS + 0x0001f044 + 0x4000 * (n))
#define GSI_EE_n_GSI_SW_VERSION_MAJOR_BMSK 0xf0000000

2
drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c
View file

@ -126,6 +126,8 @@ static int ipa_wdi_cleanup_internal(void)
struct ipa_wdi_intf_info *entry;
struct ipa_wdi_intf_info *next;
ipa3_uc_dereg_rdyCB();
/* clear interface list */
list_for_each_entry_safe(entry, next,
&ipa_wdi_ctx->head_intf_list, link) {

4
drivers/platform/msm/ipa/ipa_common_i.h
View file

@ -469,10 +469,6 @@ int ipa3_connect_mhi_pipe(struct ipa_mhi_connect_params_internal *in,
u32 *clnt_hdl);
int ipa3_disconnect_mhi_pipe(u32 clnt_hdl);
bool ipa3_mhi_stop_gsi_channel(enum ipa_client_type client);
int ipa3_qmi_enable_force_clear_datapath_send(
struct ipa_enable_force_clear_datapath_req_msg_v01 *req);
int ipa3_qmi_disable_force_clear_datapath_send(
struct ipa_disable_force_clear_datapath_req_msg_v01 *req);
int ipa3_generate_tag_process(void);
int ipa3_disable_sps_pipe(enum ipa_client_type client);
int ipa3_mhi_reset_channel_internal(enum ipa_client_type client);

73
drivers/platform/msm/ipa/ipa_v3/ipa.c
View file

@ -1866,7 +1866,16 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
if (!ipa3_is_ready()) {
IPAERR("IPA not ready, waiting for init completion\n");
wait_for_completion(&ipa3_ctx->init_completion_obj);
if (ipa3_ctx->manual_fw_load) {
if (!wait_for_completion_timeout(
&ipa3_ctx->init_completion_obj,
msecs_to_jiffies(1000))) {
IPAERR("IPA not ready, return\n");
return -ETIME;
}
} else {
wait_for_completion(&ipa3_ctx->init_completion_obj);
}
}
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
@ -7034,6 +7043,9 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
ipa3_ctx->tx_wrapper_cache_max_size = get_tx_wrapper_cache_size(
resource_p->tx_wrapper_cache_max_size);
ipa3_ctx->gsi_wdi_db_polling = resource_p->gsi_wdi_db_polling;
ipa3_ctx->ipa_config_is_auto = resource_p->ipa_config_is_auto;
ipa3_ctx->manual_fw_load = resource_p->manual_fw_load;
ipa3_ctx->max_num_smmu_cb = resource_p->max_num_smmu_cb;
if (resource_p->gsi_fw_file_name) {
ipa3_ctx->gsi_fw_file_name =
@ -7499,20 +7511,21 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
/* Create the dummy netdev for LAN RX NAPI*/
ipa3_enable_napi_netdev();
result = ipa3_wwan_init();
if (result) {
IPAERR(":ipa3_wwan_init err=%d\n", -result);
result = -ENODEV;
goto fail_wwan_init;
}
if (ipa3_ctx->platform_type != IPA_PLAT_TYPE_APQ) {
result = ipa3_wwan_init();
if (result) {
IPAERR(":ipa3_wwan_init err=%d\n", -result);
result = -ENODEV;
goto fail_wwan_init;
}
result = ipa3_rmnet_ctl_init();
if (result) {
IPAERR(":ipa3_rmnet_ctl_init err=%d\n", -result);
result = -ENODEV;
goto fail_rmnet_ctl_init;
result = ipa3_rmnet_ctl_init();
if (result) {
IPAERR(":ipa3_rmnet_ctl_init err=%d\n", -result);
result = -ENODEV;
goto fail_rmnet_ctl_init;
}
}
mutex_init(&ipa3_ctx->app_clock_vote.mutex);
return 0;
@ -7828,6 +7841,10 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
ipa_drv_res->skip_ieob_mask_wa = false;
ipa_drv_res->ipa_gpi_event_rp_ddr = false;
ipa_drv_res->gsi_wdi_db_polling = false;
ipa_drv_res->ipa_config_is_auto = false;
ipa_drv_res->manual_fw_load = false;
ipa_drv_res->max_num_smmu_cb = IPA_SMMU_CB_MAX;
/* Get IPA HW Version */
result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-ver",
&ipa_drv_res->ipa_hw_type);
@ -7933,6 +7950,13 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
ipa_drv_res->ipa_wdi2
? "True" : "False");
ipa_drv_res->ipa_config_is_auto =
of_property_read_bool(pdev->dev.of_node,
"qcom,ipa-config-is-auto");
IPADBG(": ipa-config-is-auto = %s\n",
ipa_drv_res->ipa_config_is_auto
? "True" : "False");
ipa_drv_res->ipa_wan_skb_page =
of_property_read_bool(pdev->dev.of_node,
"qcom,wan-use-skb-page");
@ -8357,6 +8381,22 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
get_dts_tx_wrapper_cache_size(pdev, ipa_drv_res);
ipa_drv_res->manual_fw_load =
of_property_read_bool(pdev->dev.of_node,
"qcom,manual-fw-load");
IPADBG(": manual-fw-load (%s)\n",
ipa_drv_res->manual_fw_load? "True" : "False");
result = of_property_read_u32(pdev->dev.of_node,
"qcom,max_num_smmu_cb",
&ipa_drv_res->max_num_smmu_cb);
if (result)
IPADBG(": using default max number of cb = %d\n",
ipa_drv_res->max_num_smmu_cb);
else
IPADBG(": found ipa_drv_res->max_num_smmu_cb = %d\n",
ipa_drv_res->max_num_smmu_cb);
return 0;
}
@ -8862,7 +8902,8 @@ static void ipa_smmu_update_fw_loader(void)
break;
}
}
if (i == IPA_SMMU_CB_MAX) {
if (i == IPA_SMMU_CB_MAX ||
ipa3_ctx->num_smmu_cb_probed == ipa3_ctx->max_num_smmu_cb) {
IPADBG("All %d CBs probed\n", IPA_SMMU_CB_MAX);
ipa_fw_load_sm_handle_event(IPA_FW_LOAD_EVNT_SMMU_DONE);
}
@ -8922,6 +8963,7 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p)
cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP);
cb->dev = dev;
smmu_info.present[IPA_SMMU_CB_AP] = true;
ipa3_ctx->num_smmu_cb_probed++;
ipa_smmu_update_fw_loader();
return 0;
@ -8935,6 +8977,7 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p)
cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN);
cb->dev = dev;
smmu_info.present[IPA_SMMU_CB_WLAN] = true;
ipa3_ctx->num_smmu_cb_probed++;
ipa_smmu_update_fw_loader();
return 0;
@ -8948,6 +8991,7 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p)
cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC);
cb->dev = dev;
smmu_info.present[IPA_SMMU_CB_UC] = true;
ipa3_ctx->num_smmu_cb_probed++;
ipa_smmu_update_fw_loader();
return 0;
@ -8961,6 +9005,7 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p)
cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_11AD);
cb->dev = dev;
smmu_info.present[IPA_SMMU_CB_11AD] = true;
ipa3_ctx->num_smmu_cb_probed++;
ipa_smmu_update_fw_loader();
return 0;

10
drivers/platform/msm/ipa/ipa_v3/ipa_i.h
View file

@ -1946,6 +1946,9 @@ struct ipa3_app_clock_vote {
* @rmnet_ctl_enable: enable pipe support fow low latency data
* @gsi_fw_file_name: GSI IPA fw file name
* @uc_fw_file_name: uC IPA fw file name
* @manual_fw_load: bool,if fw load is done manually
* @max_num_smmu_cb: number of smmu s1 cb supported
* @ipa_config_is_auto: flag to indicate auto config
*/
struct ipa3_context {
struct ipa3_char_device_context cdev;
@ -2024,6 +2027,7 @@ struct ipa3_context {
enum gsi_ver gsi_ver;
enum ipa3_platform_type platform_type;
bool ipa_config_is_mhi;
bool ipa_config_is_auto;
bool use_ipa_teth_bridge;
bool modem_cfg_emb_pipe_flt;
bool ipa_wdi2;
@ -2137,6 +2141,9 @@ struct ipa3_context {
char *uc_fw_file_name;
bool gsi_wdi_db_polling;
u32 ipa_wan_aggr_pkt_cnt;
bool manual_fw_load;
u32 num_smmu_cb_probed;
u32 max_num_smmu_cb;
};
struct ipa3_plat_drv_res {
@ -2202,6 +2209,9 @@ struct ipa3_plat_drv_res {
u32 tx_wrapper_cache_max_size;
bool gsi_wdi_db_polling;
u32 ipa_wan_aggr_pkt_cnt;
bool manual_fw_load;
bool ipa_config_is_auto;
u32 max_num_smmu_cb;
};
/**

2
drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c
View file

@ -3001,7 +3001,7 @@ int ipa3_uc_dereg_rdyCB(void)
return 0;
}
EXPORT_SYMBOL(ipa3_uc_dereg_rdyCB);
/**
* ipa3_uc_wdi_get_dbpa() - To retrieve

158
drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
View file

@ -263,6 +263,7 @@ enum ipa_ver {
IPA_4_0_MHI,
IPA_4_1,
IPA_4_1_APQ,
IPA_4_1_APQ_AUTO,
IPA_4_2,
IPA_4_5,
IPA_4_5_MHI,
@ -374,6 +375,19 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config
[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
{14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },
},
[IPA_4_1_APQ_AUTO] = {
/* LWA_DL UL_DL unused UC_RX_Q, other are invalid */
[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
{1, 63}, {1, 63}, {0, 0}, {1, 63}, {0, 0}, {0, 0} },
[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = {
{10, 10}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} },
[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
{12, 12}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} },
[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
{0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0}, {0, 0} },
[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
{14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },
},
[IPA_4_2] = {
/* UL_DL other are invalid */
[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
@ -521,6 +535,13 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
{2, 63}, {1, 63}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
},
[IPA_4_1_APQ_AUTO] = {
/* LWA_DL UL/DL/DPL uC, other are invalid */
[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
{4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} },
[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
{2, 63}, {1, 63}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
},
[IPA_4_2] = {
/* UL/DL/DPL, other are invalid */
[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
@ -610,6 +631,11 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
{3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },
},
[IPA_4_1_APQ_AUTO] = {
/* LWA_DL UL_DL unused UC_RX_Q, other are invalid */
[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
{3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },
},
[IPA_4_2] = {
/* UL_DL, other are invalid */
[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
@ -713,6 +739,8 @@ static const struct ipa_qmb_outstanding ipa3_qmb_outstanding
[IPA_4_0_MHI][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0},
[IPA_4_1][IPA_QMB_INSTANCE_DDR] = {12, 8, 120},
[IPA_4_1][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0},
[IPA_4_1_APQ_AUTO][IPA_QMB_INSTANCE_DDR] = {12, 8, 120},
[IPA_4_1_APQ_AUTO][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0},
[IPA_4_2][IPA_QMB_INSTANCE_DDR] = {12, 8, 0},
[IPA_4_5][IPA_QMB_INSTANCE_DDR] = {16, 8, 120},
[IPA_4_5][IPA_QMB_INSTANCE_PCIE] = {12, 8, 0},
@ -2033,6 +2061,126 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
QMB_MASTER_SELECT_DDR,
{ 17, 14, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_WLAN2_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
true,
IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
QMB_MASTER_SELECT_DDR,
{ 6, 11, 8, 16, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_USB_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
true,
IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
QMB_MASTER_SELECT_DDR,
{ 0, 8, 8, 16, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_APPS_LAN_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
QMB_MASTER_SELECT_DDR,
{ 8, 10, 8, 16, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_APPS_CMD_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
QMB_MASTER_SELECT_DDR,
{ 5, 4, 20, 24, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_ETHERNET_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
true,
IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
QMB_MASTER_SELECT_DDR,
{ 9, 0, 8, 16, IPA_EE_UC } },
/* Only for test purpose */
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
true,
IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
QMB_MASTER_SELECT_DDR,
{0, 8, 8, 16, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST1_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
true,
IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
QMB_MASTER_SELECT_DDR,
{ 0, 8, 8, 16, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST2_PROD] = {
true, IPA_v4_0_GROUP_UL_DL,
true,
IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
QMB_MASTER_SELECT_DDR,
{ 6, 2, 8, 16, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_WLAN2_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 18, 15, 8, 13, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_USB_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 19, 12, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_USB_DPL_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 15, 7, 5, 5, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_APPS_LAN_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 10, 5, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_ODL_DPL_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 12, 2, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_ETHERNET_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 22, 1, 9, 9, IPA_EE_UC } },
/* Only for test purpose */
/* MBIM aggregation test pipes should have the same QMB as USB_CONS */
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 19, 12, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST1_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 19, 12, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST2_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 18, 3, 9, 9, IPA_EE_AP } },
[IPA_4_1_APQ_AUTO][IPA_CLIENT_TEST3_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 15, 7, 5, 5, IPA_EE_AP } },
/* Dummy consumer (pipe 31) is used in L2TP rt rule */
[IPA_4_1_APQ_AUTO][IPA_CLIENT_DUMMY_CONS] = {
true, IPA_v4_0_GROUP_UL_DL,
false,
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 31, 31, 8, 8, IPA_EE_AP } },
/* IPA_4_2 */
[IPA_4_2][IPA_CLIENT_WLAN1_PROD] = {
true, IPA_v4_2_GROUP_UL_DL,
@ -4459,6 +4607,12 @@ u8 ipa3_get_hw_type_index(void)
break;
case IPA_HW_v4_1:
hw_type_index = IPA_4_1;
if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) {
hw_type_index = IPA_4_1_APQ;
if (ipa3_ctx->ipa_config_is_auto) {
hw_type_index = IPA_4_1_APQ_AUTO;
}
}
break;
case IPA_HW_v4_2:
hw_type_index = IPA_4_2;
@ -7888,6 +8042,8 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index,
case IPA_4_0:
case IPA_4_0_MHI:
case IPA_4_1:
case IPA_4_1_APQ:
case IPA_4_1_APQ_AUTO:
if (src) {
switch (group_index) {
case IPA_v4_0_GROUP_LWA_DL:
@ -8253,6 +8409,8 @@ void ipa3_set_resorce_groups_min_max_limits(void)
case IPA_4_0:
case IPA_4_0_MHI:
case IPA_4_1:
case IPA_4_1_APQ:
case IPA_4_1_APQ_AUTO:
src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX;
dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX;
src_grp_idx_max = IPA_v4_0_SRC_GROUP_MAX;