From 831f7d54a7172a4e54f20e45d70b9270ba71e83a Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 10 Mar 2020 19:22:41 -0700 Subject: [PATCH] ARM: dts: msm: enable secondary DSI display for lahaina Change enables secondary DSI display for lahaina target. Change-Id: I77869965a807ef2189ac4c5a822d45288c635bfa --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 3 ++ display/lahaina-sde-display-cdp.dtsi | 19 ++++++++- display/lahaina-sde-display-mtp.dtsi | 11 ++++++ display/lahaina-sde-display.dtsi | 47 ++++++++++++++++++++++- 4 files changed, 78 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi index 1d9d3e26f7cf..f5bb6a05fea2 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -14,6 +14,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; qcom,mdss-dsi-bllp-eof-power-mode; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 5e6288b7d302..909a24d435b7 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -21,12 +21,15 @@ &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_video { @@ -114,11 +117,14 @@ &dsi_nt35695b_truly_fhd_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_sim_cmd { @@ -163,7 +169,18 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; +}; + + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; - diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 8643ec14d181..1670754abfd0 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -61,6 +61,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 5d64f743a336..8816b03298ea 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -154,6 +154,34 @@ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; + + qcom,mdp = <&mdss_mdp>; + }; + sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -162,7 +190,7 @@ }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_rscc>; + connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; /* PHY TIMINGS REVISION YB */ @@ -230,6 +258,7 @@ &dsi_r66451_amoled_cmd { qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 08 07 0c 0b 07 @@ -489,6 +518,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 @@ -791,3 +821,18 @@ }; }; }; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +};