diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c
index a2e8d88de1d8..cf4b9f8fccc8 100644
--- a/drivers/pci/controller/pci-msm.c
+++ b/drivers/pci/controller/pci-msm.c
@@ -106,8 +106,6 @@
 #define PCIE_IATU_UTAR(n) (PCIE_IATU_BASE(n) + 0x18)
 
 #define PCIE20_PORT_LINK_CTRL_REG (0x710)
-#define PCIE20_PIPE_LOOPBACK_CONTROL (0x8b8)
-#define LOOPBACK_BASE_ADDR_OFFSET (0x8000)
 
 #define PCIE20_CTRL1_TYPE_CFG0 (0x04)
 #define PCIE20_CTRL1_TYPE_CFG1 (0x05)
@@ -425,15 +423,6 @@ enum msm_pcie_debugfs_option {
 	MSM_PCIE_READ_PCIE_REGISTER,
 	MSM_PCIE_WRITE_PCIE_REGISTER,
 	MSM_PCIE_DUMP_PCIE_REGISTER_SPACE,
-	MSM_PCIE_ALLOCATE_DDR_MAP_LBAR,
-	MSM_PCIE_FREE_DDR_UNMAP_LBAR,
-	MSM_PCIE_OUTPUT_DDR_LBAR_ADDRESS,
-	MSM_PCIE_CONFIGURE_LOOPBACK,
-	MSM_PCIE_SETUP_LOOPBACK_IATU,
-	MSM_PCIE_READ_DDR,
-	MSM_PCIE_READ_LBAR,
-	MSM_PCIE_WRITE_DDR,
-	MSM_PCIE_WRITE_LBAR,
 	MSM_PCIE_DISABLE_AER,
 	MSM_PCIE_ENABLE_AER,
 	MSM_PCIE_GPIO_STATUS,
@@ -463,15 +452,6 @@ static const char * const
 	"READ A PCIE REGISTER",
 	"WRITE TO PCIE REGISTER",
 	"DUMP PCIE REGISTER SPACE",
-	"ALLOCATE DDR AND MAP LBAR",
-	"FREE DDR AND UNMAP LBAR",
-	"OUTPUT DDR AND LBAR VIR ADDRESS",
-	"CONFIGURE PCIE LOOPBACK",
-	"SETUP LOOPBACK IATU",
-	"READ DDR",
-	"READ LBAR",
-	"WRITE DDR",
-	"WRITE LBAR",
 	"SET AER ENABLE FLAG",
 	"CLEAR AER ENABLE FLAG",
 	"OUTPUT PERST AND WAKE GPIO STATUS",
@@ -1375,14 +1355,6 @@ static void msm_pcie_shadow_dump(struct msm_pcie_dev_t *dev, bool rc)
 static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
 					u32 testcase)
 {
-	u32 dbi_base_addr = dev->res[MSM_PCIE_RES_DM_CORE].resource->start;
-	phys_addr_t loopback_lbar_phy =
-		dev->res[MSM_PCIE_RES_DM_CORE].resource->start +
-		LOOPBACK_BASE_ADDR_OFFSET;
-	static uint32_t loopback_val = 0x1;
-	static dma_addr_t loopback_ddr_phy;
-	static uint32_t *loopback_ddr_vir;
-	static void __iomem *loopback_lbar_vir;
 	int ret, i;
 	u32 base_sel_size = 0;
 	u32 wr_ofst = 0;
@@ -1640,328 +1612,6 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
 			readl_relaxed(dev->res[base_sel - 1].base + (i + 28)));
 		}
 		break;
-	case MSM_PCIE_ALLOCATE_DDR_MAP_LBAR:
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: Allocate 4K DDR memory and map LBAR.\n",
-			dev->rc_idx);
-		loopback_ddr_vir = dma_alloc_coherent(&dev->pdev->dev,
-			(SZ_1K * sizeof(*loopback_ddr_vir)),
-			&loopback_ddr_phy, GFP_KERNEL);
-		if (!loopback_ddr_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: failed to dma_alloc_coherent.\n",
-				dev->rc_idx);
-		} else {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: VIR DDR memory address: 0x%pK\n",
-				dev->rc_idx, loopback_ddr_vir);
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: PHY DDR memory address: %pad\n",
-				dev->rc_idx, &loopback_ddr_phy);
-		}
-
-		PCIE_DBG_FS(dev, "PCIe: RC%d: map LBAR: %pa\n",
-			dev->rc_idx, &loopback_lbar_phy);
-		loopback_lbar_vir = devm_ioremap(&dev->pdev->dev,
-			loopback_lbar_phy, SZ_4K);
-		if (!loopback_lbar_vir) {
-			PCIE_DBG_FS(dev, "PCIe: RC%d: failed to map %pa\n",
-				dev->rc_idx, &loopback_lbar_phy);
-		} else {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: successfully mapped %pa to 0x%pK\n",
-				dev->rc_idx, &loopback_lbar_phy,
-				loopback_lbar_vir);
-		}
-		break;
-	case MSM_PCIE_FREE_DDR_UNMAP_LBAR:
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: Release 4K DDR memory and unmap LBAR.\n",
-			dev->rc_idx);
-
-		if (loopback_ddr_vir) {
-			dma_free_coherent(&dev->pdev->dev, SZ_4K,
-				loopback_ddr_vir, loopback_ddr_phy);
-			loopback_ddr_vir = NULL;
-		}
-
-		if (loopback_lbar_vir) {
-			devm_iounmap(&dev->pdev->dev,
-				loopback_lbar_vir);
-			loopback_lbar_vir = NULL;
-		}
-		break;
-	case MSM_PCIE_OUTPUT_DDR_LBAR_ADDRESS:
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: Print DDR and LBAR addresses.\n",
-			dev->rc_idx);
-
-		if (!loopback_ddr_vir || !loopback_lbar_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: DDR or LBAR address is not mapped\n",
-				dev->rc_idx);
-			break;
-		}
-
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PHY DDR address: %pad\n",
-			dev->rc_idx, &loopback_ddr_phy);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: VIR DDR address: 0x%pK\n",
-			dev->rc_idx, loopback_ddr_vir);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PHY LBAR address: %pa\n",
-			dev->rc_idx, &loopback_lbar_phy);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: VIR LBAR address: 0x%pK\n",
-			dev->rc_idx, loopback_lbar_vir);
-		break;
-	case MSM_PCIE_CONFIGURE_LOOPBACK:
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: Configure Loopback.\n",
-			dev->rc_idx);
-
-		writel_relaxed(0x10000,
-			dev->dm_core + PCIE_GEN3_RELATED);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: 0x%x: 0x%x\n",
-			dev->rc_idx,
-			dbi_base_addr + PCIE_GEN3_RELATED,
-			readl_relaxed(dev->dm_core +
-				PCIE_GEN3_RELATED));
-
-		writel_relaxed(0x80000001,
-			dev->dm_core + PCIE20_PIPE_LOOPBACK_CONTROL);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: 0x%x: 0x%x\n",
-			dev->rc_idx,
-			dbi_base_addr + PCIE20_PIPE_LOOPBACK_CONTROL,
-			readl_relaxed(dev->dm_core +
-				PCIE20_PIPE_LOOPBACK_CONTROL));
-
-		writel_relaxed(0x00010124,
-			dev->dm_core + PCIE20_PORT_LINK_CTRL_REG);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: 0x%x: 0x%x\n",
-			dev->rc_idx,
-			dbi_base_addr + PCIE20_PORT_LINK_CTRL_REG,
-			readl_relaxed(dev->dm_core +
-				PCIE20_PORT_LINK_CTRL_REG));
-		break;
-	case MSM_PCIE_SETUP_LOOPBACK_IATU:
-	{
-		void __iomem *iatu_base_vir;
-		u32 iatu_base_phy;
-		u32 iatu_viewport_offset;
-		u32 iatu_ctrl1_offset;
-		u32 iatu_ctrl2_offset;
-		u32 iatu_lbar_offset;
-		u32 iatu_ubar_offset;
-		u32 iatu_lar_offset;
-		u32 iatu_ltar_offset;
-		u32 iatu_utar_offset;
-		u32 iatu_n = 1;
-
-		if (dev->iatu) {
-			iatu_base_vir = dev->iatu;
-			iatu_base_phy =
-				dev->res[MSM_PCIE_RES_IATU].resource->start;
-
-			iatu_viewport_offset = 0;
-			iatu_ctrl1_offset = PCIE_IATU_CTRL1(iatu_n);
-			iatu_ctrl2_offset = PCIE_IATU_CTRL2(iatu_n);
-			iatu_lbar_offset = PCIE_IATU_LBAR(iatu_n);
-			iatu_ubar_offset = PCIE_IATU_UBAR(iatu_n);
-			iatu_lar_offset = PCIE_IATU_LAR(iatu_n);
-			iatu_ltar_offset = PCIE_IATU_LTAR(iatu_n);
-			iatu_utar_offset = PCIE_IATU_UTAR(iatu_n);
-		} else {
-			iatu_base_vir = dev->dm_core;
-			iatu_base_phy = dbi_base_addr;
-
-			iatu_viewport_offset = PCIE20_PLR_IATU_VIEWPORT;
-			iatu_ctrl1_offset = PCIE20_PLR_IATU_CTRL1;
-			iatu_ctrl2_offset = PCIE20_PLR_IATU_CTRL2;
-			iatu_lbar_offset = PCIE20_PLR_IATU_LBAR;
-			iatu_ubar_offset = PCIE20_PLR_IATU_UBAR;
-			iatu_lar_offset = PCIE20_PLR_IATU_LAR;
-			iatu_ltar_offset = PCIE20_PLR_IATU_LTAR;
-			iatu_utar_offset = PCIE20_PLR_IATU_UTAR;
-		}
-
-		PCIE_DBG_FS(dev, "PCIe: RC%d: Setup iATU.\n", dev->rc_idx);
-
-		if (!loopback_ddr_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: DDR address is not mapped.\n",
-				dev->rc_idx);
-			break;
-		}
-
-		if (iatu_viewport_offset) {
-			writel_relaxed(0x0, iatu_base_vir +
-				iatu_viewport_offset);
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: PCIE20_PLR_IATU_VIEWPORT:\t0x%x: 0x%x\n",
-				dev->rc_idx,
-				iatu_base_phy + iatu_viewport_offset,
-				readl_relaxed(iatu_base_vir +
-					iatu_viewport_offset));
-		}
-
-		writel_relaxed(0x0, iatu_base_vir + iatu_ctrl1_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_CTRL1:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_ctrl1_offset,
-			readl_relaxed(iatu_base_vir + iatu_ctrl1_offset));
-
-		writel_relaxed(loopback_lbar_phy,
-			iatu_base_vir + iatu_lbar_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_LBAR:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_lbar_offset,
-			readl_relaxed(iatu_base_vir + iatu_lbar_offset));
-
-		writel_relaxed(0x0, iatu_base_vir + iatu_ubar_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_UBAR:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_ubar_offset,
-			readl_relaxed(iatu_base_vir + iatu_ubar_offset));
-
-		writel_relaxed(loopback_lbar_phy + 0xfff,
-			iatu_base_vir + iatu_lar_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_LAR:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_lar_offset,
-			readl_relaxed(iatu_base_vir + iatu_lar_offset));
-
-		writel_relaxed(loopback_ddr_phy,
-			iatu_base_vir + iatu_ltar_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_LTAR:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_ltar_offset,
-			readl_relaxed(iatu_base_vir + iatu_ltar_offset));
-
-		writel_relaxed(0, iatu_base_vir + iatu_utar_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_UTAR:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_utar_offset,
-			readl_relaxed(iatu_base_vir + iatu_utar_offset));
-
-		writel_relaxed(0x80000000,
-			iatu_base_vir + iatu_ctrl2_offset);
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: PCIE20_PLR_IATU_CTRL2:\t0x%x: 0x%x\n",
-			dev->rc_idx, iatu_base_phy + iatu_ctrl2_offset,
-			readl_relaxed(iatu_base_vir + iatu_ctrl2_offset));
-		break;
-	}
-	case MSM_PCIE_READ_DDR:
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: Read DDR values.\n",
-			dev->rc_idx);
-
-		if (!loopback_ddr_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: DDR is not mapped\n",
-				dev->rc_idx);
-			break;
-		}
-
-		for (i = 0; i < SZ_1K; i += 8) {
-			PCIE_DBG_FS(dev,
-				"0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n",
-				i,
-				loopback_ddr_vir[i],
-				loopback_ddr_vir[i + 1],
-				loopback_ddr_vir[i + 2],
-				loopback_ddr_vir[i + 3],
-				loopback_ddr_vir[i + 4],
-				loopback_ddr_vir[i + 5],
-				loopback_ddr_vir[i + 6],
-				loopback_ddr_vir[i + 7]);
-		}
-		break;
-	case MSM_PCIE_READ_LBAR:
-		PCIE_DBG_FS(dev,
-			"PCIe: RC%d: Read LBAR values.\n",
-			dev->rc_idx);
-
-		if (!loopback_lbar_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: LBAR address is not mapped\n",
-				dev->rc_idx);
-			break;
-		}
-
-		for (i = 0; i < SZ_4K; i += 32) {
-			PCIE_DBG_FS(dev,
-				"0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n",
-				i,
-				readl_relaxed(loopback_lbar_vir + i),
-				readl_relaxed(loopback_lbar_vir + (i + 4)),
-				readl_relaxed(loopback_lbar_vir + (i + 8)),
-				readl_relaxed(loopback_lbar_vir + (i + 12)),
-				readl_relaxed(loopback_lbar_vir + (i + 16)),
-				readl_relaxed(loopback_lbar_vir + (i + 20)),
-				readl_relaxed(loopback_lbar_vir + (i + 24)),
-				readl_relaxed(loopback_lbar_vir + (i + 28)));
-		}
-		break;
-	case MSM_PCIE_WRITE_DDR:
-		PCIE_DBG_FS(dev, "PCIe: RC%d: Write 0x%x to DDR.\n",
-			dev->rc_idx, loopback_val);
-
-		if (!loopback_ddr_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: DDR address is not mapped\n",
-				dev->rc_idx);
-			break;
-		}
-
-		memset(loopback_ddr_vir, loopback_val,
-			(SZ_1K * sizeof(*loopback_ddr_vir)));
-
-		if (unlikely(loopback_val == UINT_MAX))
-			loopback_val = 1;
-		else
-			loopback_val++;
-		break;
-	case MSM_PCIE_WRITE_LBAR:
-		PCIE_DBG_FS(dev, "PCIe: RC%d: Write 0x%x to LBAR.\n",
-			dev->rc_idx, loopback_val);
-
-		if (!loopback_lbar_vir) {
-			PCIE_DBG_FS(dev,
-				"PCIe: RC%d: LBAR address is not mapped\n",
-				dev->rc_idx);
-			break;
-		}
-
-		for (i = 0; i < SZ_4K; i += 32) {
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + i),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 4)),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 8)),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 12)),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 16)),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 20)),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 24)),
-			writel_relaxed(loopback_val,
-				loopback_lbar_vir + (i + 28));
-		}
-
-		if (unlikely(loopback_val == UINT_MAX))
-			loopback_val = 1;
-		else
-			loopback_val++;
-		break;
 	case MSM_PCIE_DISABLE_AER:
 		PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: clear AER enable flag\n\n",
 			dev->rc_idx);