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ARM: 8278/1: sa1100: split irq handling for low GPIOs

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Low GPIO pins use an interrupt in SC interrupts space. However it's
possible to handle them as if all the GPIO interrupts are instead tied
to single GPIO handler, which later decodes GEDR register and
chain-calls next IRQ handler. So split first 11 interrupts into system
part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
system controller interrupts and real GPIO interrupts
(IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
decodes and calls next handler.

Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Dmitry Eremin-Solenikov 2015-01-15 02:29:16 +01:00 • committed by Russell King
commit 83508093f4
3 changed files with 93 additions and 69 deletions
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2
drivers/gpio/gpio-sa1100.c
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@ -50,7 +50,7 @@ static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int
static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
{
return offset < 11 ? (IRQ_GPIO0 + offset) : (IRQ_GPIO11 - 11 + offset);
return IRQ_GPIO0 + offset;
}
static struct gpio_chip sa1100_gpio_chip = {