mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Minor manual fixups for gfp_t clashes.
This commit is contained in:
Linus Torvalds
commit
83928e17b9
138 changed files with 4715 additions and 782 deletions
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@ -17,6 +17,16 @@
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|||
#error You must include hardware.h not this file
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#endif /* __ASM_ARCH_HARDWARE_H */
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||||
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/* Chip selects */
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#define AAEC_CS0 0x00000000
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#define AAEC_CS1 0x10000000
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#define AAEC_CS2 0x20000000
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#define AAEC_CS3 0x30000000
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/* Flash */
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#define AAEC_FLASH_BASE AAEC_CS0
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#define AAEC_FLASH_SIZE SZ_64M
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/* Interrupt controller */
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#define IRQ_BASE __REG(0x80000500)
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#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
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@ -148,4 +158,50 @@
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#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
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#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
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/* GPIO Registers */
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#define AAEC_GPIO_PHYS 0x80000e00
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#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
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#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
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#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
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#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
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#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
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#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
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#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
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#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
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#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
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#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
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#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
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#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
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#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
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#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
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#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
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#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
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#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
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#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
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#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
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#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
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#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
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#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
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#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
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#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
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#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
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#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
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#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
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#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
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#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
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#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
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#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
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#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
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#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
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#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)
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#define AAEC_GPIO_PINMUX_PE0CON (1 << 0)
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#define AAEC_GPIO_PINMUX_PD0CON (1 << 1)
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#define AAEC_GPIO_PINMUX_CODECON (1 << 2)
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#define AAEC_GPIO_PINMUX_UART3CON (1 << 3)
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/* LCD Controller */
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#define AAEC_CLCD_PHYS 0x80003000
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#endif /* __ARM_ARCH_AAEC2000_H */
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40
include/asm-arm/arch-aaec2000/aaed2000.h
Normal file
40
include/asm-arm/arch-aaec2000/aaed2000.h
Normal file
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@ -0,0 +1,40 @@
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/*
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* linux/include/asm-arm/arch-aaec2000/aaed2000.h
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*
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* AAED-2000 specific bits definition
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*
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* Copyright (c) 2005 Nicolas Bellido Y Ortega
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_AAED2000_H
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#define __ASM_ARCH_AAED2000_H
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/* External GPIOs. */
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#define EXT_GPIO_PBASE AAEC_CS3
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#define EXT_GPIO_VBASE 0xf8100000
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#define EXT_GPIO_LENGTH 0x00001000
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#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
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#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
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#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x)))
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#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x)))
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#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE)
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#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */
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#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */
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#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */
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#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */
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#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */
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#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */
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#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */
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#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */
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#endif /* __ARM_ARCH_AAED2000_H */
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@ -11,7 +11,8 @@
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <linux/config.h>
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#include <asm/sizes.h>
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#include <asm/arch/aaec2000.h>
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/* The kernel is loaded at physical address 0xf8000000.
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* We map the IO space a bit after
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@ -6,6 +6,8 @@
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <asm/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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@ -10,6 +10,8 @@
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <asm/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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@ -235,4 +235,121 @@
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#define CEIVA_PB0_BLK_BTN (1<<0)
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#endif // #if defined (CONFIG_ARCH_CEIVA)
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#if defined (CONFIG_MACH_MP1000)
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/* NOR FLASH */
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#define MP1000_NIO_BASE 0xf9000000 /* virtual */
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#define MP1000_NIO_START CS0_PHYS_BASE /* physical */
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#define MP1000_NIO_SIZE 0x00400000
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/* DSP Interface */
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#define MP1000_DSP_BASE 0xfa000000 /* virtual */
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#define MP1000_DSP_START CS1_PHYS_BASE /* physical */
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#define MP1000_DSP_SIZE 0x00100000
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/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
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#define MP1000_LIO_BASE 0xfb000000 /* virtual */
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#define MP1000_LIO_START CS2_PHYS_BASE /* physical */
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#define MP1000_LIO_SIZE 0x00100000
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/* NAND FLASH */
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#define MP1000_FIO_BASE 0xfc000000 /* virtual */
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#define MP1000_FIO_START CS3_PHYS_BASE /* physical */
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#define MP1000_FIO_SIZE 0x00800000
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/* Ethernet */
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#define MP1000_EIO_BASE 0xfd000000 /* virtual */
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#define MP1000_EIO_START CS4_PHYS_BASE /* physical */
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#define MP1000_EIO_SIZE 0x00100000
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#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
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#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
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#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
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#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
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/* IDE */
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#define MP1000_IDE_BASE 0xfe000000 /* virtual */
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#define MP1000_IDE_START CS5_PHYS_BASE /* physical */
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#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
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#define IRQ_HARDDISK IRQ_EINT2
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/*
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* IDE registers definition
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*/
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#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
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#define IDE_BASE_OFF (MP1000_IDE_BASE)
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#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
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#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
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#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
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#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
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#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
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#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
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#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
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#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
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#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
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#define IDE_IRQ IRQ_EINT2
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#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
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#define RTC_ALWAYS_BCD 0
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/*
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// Definitions of the bit fields in the HwPortA register for the
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// MP1000 board.
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*/
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#define HwPortAKeyboardRow1 0x00000001
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#define HwPortAKeyboardRow2 0x00000002
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#define HwPortAKeyboardRow3 0x00000004
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#define HwPortAKeyboardRow4 0x00000008
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#define HwPortAKeyboardRow5 0x00000010
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#define HwPortAKeyboardRow6 0x00000020
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#define HwPortALCDEnable 0x00000040
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#define HwPortAOffhook 0x00000080
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/*
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// Definitions of the bit fields in the HwPortB register for the
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// MP1000 board.
|
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*/
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#define HwPortBL3Mode 0x00000001
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#define HwPortBL3Clk 0x00000002
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#define HwPortBSClk 0x00000001
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#define HwPortBSData 0x00000002
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#define HwPortBL3Data 0x00000004
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#define HwPortBMute 0x00000008
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#define HwPortBQD0 0x00000010
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#define HwPortBQD1 0x00000020
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#define HwPortBQD2 0x00000040
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#define HwPortBQD3 0x00000080
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|
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/*
|
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// Definitions of the bit fields in the HwPortD register for the
|
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// MP1000 board.
|
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*/
|
||||
#define HwPortDLED1 0x00000001
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#define HwPortDLED2 0x00000002
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#define HwPortDLED3 0x00000004
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#define HwPortDLED4 0x00000008
|
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#define HwPortDLED5 0x00000010
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#define HwPortDEECS 0x00000020
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#define HwPortBRTS 0x00000040
|
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#define HwPortBRI 0x00000080
|
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|
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|
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/*
|
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// Definitions of the bit fields in the HwPortE register for the
|
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// MP1000 board.
|
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*/
|
||||
|
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#define HwPortECLE 0x00000001
|
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#define HwPortESepromDOut 0x00000001
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#define HwPortEALE 0x00000002
|
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#define HwPortESepromDIn 0x00000002
|
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#define HwPortENANDCS 0x00000004
|
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#define HwPortESepromCLK 0x00000004
|
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|
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#endif // #if defined (CONFIG_MACH_MP1000)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(a) ((void __iomem *)(a))
|
||||
|
|
|
|||
77
include/asm-arm/arch-clps711x/mp1000-seprom.h
Normal file
77
include/asm-arm/arch-clps711x/mp1000-seprom.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
#ifndef MP1000_SEPROM_H
|
||||
#define MP1000_SEPROM_H
|
||||
|
||||
/*
|
||||
* mp1000-seprom.h
|
||||
*
|
||||
*
|
||||
* This file contains the Serial EEPROM definitions for the MP1000 board
|
||||
*
|
||||
* Copyright (C) 2005 Comdial Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#define COMMAND_ERASE (0x1C0)
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#define COMMAND_ERASE_ALL (0x120)
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#define COMMAND_WRITE_DISABLE (0x100)
|
||||
#define COMMAND_WRITE_ENABLE (0x130)
|
||||
#define COMMAND_READ (0x180)
|
||||
#define COMMAND_WRITE (0x140)
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||||
#define COMMAND_WRITE_ALL (0x110)
|
||||
|
||||
//
|
||||
// Serial EEPROM data format
|
||||
//
|
||||
|
||||
#define PACKED __attribute__ ((packed))
|
||||
|
||||
typedef struct _EEPROM {
|
||||
union {
|
||||
unsigned char eprom_byte_data[128];
|
||||
unsigned short eprom_short_data[64];
|
||||
struct {
|
||||
unsigned char version PACKED; // EEPROM Version "1" for now
|
||||
unsigned char box_id PACKED; // Box ID (Standalone, SOHO, embedded, etc)
|
||||
unsigned char major_hw_version PACKED; // Major Hardware version (Hex)
|
||||
unsigned char minor_hw_version PACKED; // Minor Hardware Version (Hex)
|
||||
unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
|
||||
unsigned char mfg_serial_number[10] PACKED; // Manufacturer Serial number
|
||||
unsigned char mfg_date[3] PACKED; // Date of Mfg (Formatted YY:MM:DD)
|
||||
unsigned char country PACKED; // Country of deployment
|
||||
unsigned char mac_Address[6] PACKED; // MAC Address
|
||||
unsigned char oem_string[20] PACKED; // OEM ID string
|
||||
unsigned short feature_bits1 PACKED; // Feature Bits 1
|
||||
unsigned short feature_bits2 PACKED; // Feature Bits 2
|
||||
unsigned char filler[75] PACKED; // Unused/Undefined “0” initialized
|
||||
unsigned short checksum PACKED; // byte accumulated short checksum
|
||||
} eprom_struct;
|
||||
} variant;
|
||||
} eeprom_struct;
|
||||
|
||||
/* These settings must be mutually exclusive */
|
||||
#define FEATURE_BITS1_DRAMSIZE_16MEG 0x0001 /* 0 signifies 4 MEG system */
|
||||
#define FEATURE_BITS1_DRAMSIZE_8MEG 0x0002 /* 1 in bit 1 = 8MEG system */
|
||||
#define FEATURE_BITS1_DRAMSIZE_64MEG 0x0004 /* 1 in bit 2 = 64MEG system */
|
||||
|
||||
#define FEATURE_BITS1_CPUIS90MEG 0x0010
|
||||
|
||||
extern void seprom_init(void);
|
||||
extern eeprom_struct* get_seprom_ptr(void);
|
||||
extern unsigned char* get_eeprom_mac_address(void);
|
||||
|
||||
#endif /* MP1000_SEPROM_H */
|
||||
|
||||
|
|
@ -14,6 +14,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffff
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffff
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(a) ((void __iomem *)(a))
|
||||
|
|
|
|||
|
|
@ -33,15 +33,6 @@
|
|||
#define IO_SIZE 0x0B000000 // How much?
|
||||
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
|
||||
|
||||
/*
|
||||
* Similar to above, but for PCI addresses (memory, IO, Config and the
|
||||
* V3 chip itself). WARNING: this has to mirror definitions in platform.h
|
||||
*/
|
||||
#define PCI_MEMORY_VADDR 0xe8000000
|
||||
#define PCI_CONFIG_VADDR 0xec000000
|
||||
#define PCI_V3_VADDR 0xed000000
|
||||
#define PCI_IO_VADDR 0xee000000
|
||||
|
||||
#define PCIO_BASE PCI_IO_VADDR
|
||||
#define PCIMEM_BASE PCI_MEMORY_VADDR
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,14 @@
|
|||
|
||||
#define IO_SPACE_LIMIT 0xffff
|
||||
|
||||
/*
|
||||
* WARNING: this has to mirror definitions in platform.h
|
||||
*/
|
||||
#define PCI_MEMORY_VADDR 0xe8000000
|
||||
#define PCI_CONFIG_VADDR 0xec000000
|
||||
#define PCI_V3_VADDR 0xed000000
|
||||
#define PCI_IO_VADDR 0xee000000
|
||||
|
||||
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
|
||||
#define __mem_pci(a) (a)
|
||||
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(p) ((void __iomem *)(p))
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
|
|
|
|||
|
|
@ -392,4 +392,47 @@
|
|||
#define WDT_RESET_ENABLE 0x01000000
|
||||
|
||||
|
||||
/*
|
||||
* MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
|
||||
* units, but the registers that differ between the two don't overlap,
|
||||
* so we can have one register list for both.
|
||||
*/
|
||||
#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
|
||||
#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
|
||||
#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
|
||||
#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
|
||||
#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
|
||||
#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
|
||||
#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
|
||||
#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
|
||||
#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
|
||||
#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
|
||||
#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
|
||||
#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
|
||||
#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
|
||||
#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
|
||||
#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
|
||||
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
|
||||
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
|
||||
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
|
||||
#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
|
||||
#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
|
||||
#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
|
||||
#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
|
||||
#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
|
||||
#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
|
||||
#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
|
||||
#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
|
||||
#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
|
||||
#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
|
||||
#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
|
||||
#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
|
||||
#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
|
||||
#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
|
||||
#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
|
||||
#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
|
||||
#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
|
||||
#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
|
||||
|
||||
|
||||
#endif /* _IXP2000_H_ */
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/* No ISA or PCI bus on this machine. */
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -44,12 +44,12 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
|
||||
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
|
||||
|
||||
/* With indexed regs we don't want to feed the index through io_p2v()
|
||||
especially if it is a variable, otherwise horrible code will result. */
|
||||
# define __REG2(x,y) \
|
||||
(*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
|
||||
(*(volatile u32 *)((u32)&__REG(x) + (y)))
|
||||
|
||||
# define __PREG(x) (io_v2p((u32)&(x)))
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
|
|
|
|||
17
include/asm-arm/arch-pxa/irda.h
Normal file
17
include/asm-arm/arch-pxa/irda.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
#ifndef ASMARM_ARCH_IRDA_H
|
||||
#define ASMARM_ARCH_IRDA_H
|
||||
|
||||
/* board specific transceiver capabilities */
|
||||
|
||||
#define IR_OFF 1
|
||||
#define IR_SIRMODE 2
|
||||
#define IR_FIRMODE 4
|
||||
|
||||
struct pxaficp_platform_data {
|
||||
int transceiver_cap;
|
||||
void (*transceiver_mode)(struct device *dev, int mode);
|
||||
};
|
||||
|
||||
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
|
||||
|
||||
#endif
|
||||
|
|
@ -326,6 +326,25 @@
|
|||
#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Hardware UART (HWUART) */
|
||||
#define HWUART HWRBR
|
||||
#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
|
||||
#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
|
||||
#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
|
||||
#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
|
||||
#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
|
||||
#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
|
||||
#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
|
||||
#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
|
||||
#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
|
||||
#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
|
||||
#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
|
||||
#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
|
||||
#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
|
||||
#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
|
||||
#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
|
||||
#define IER_UUE (1 << 6) /* UART Unit Enable */
|
||||
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
|
||||
|
|
@ -1013,14 +1032,12 @@
|
|||
#define ICCR0_LBM (1 << 1) /* Loopback mode */
|
||||
#define ICCR0_ITR (1 << 0) /* IrDA transmission */
|
||||
|
||||
#ifdef CONFIG_PXA27x
|
||||
#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
|
||||
#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
|
||||
#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
|
||||
#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
|
||||
#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
|
||||
#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PXA27x
|
||||
#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
|
||||
|
|
@ -1250,9 +1267,13 @@
|
|||
#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
|
||||
#define GPIO41_FFRTS 41 /* FFUART request to send */
|
||||
#define GPIO42_BTRXD 42 /* BTUART receive data */
|
||||
#define GPIO42_HWRXD 42 /* HWUART receive data */
|
||||
#define GPIO43_BTTXD 43 /* BTUART transmit data */
|
||||
#define GPIO43_HWTXD 43 /* HWUART transmit data */
|
||||
#define GPIO44_BTCTS 44 /* BTUART clear to send */
|
||||
#define GPIO44_HWCTS 44 /* HWUART clear to send */
|
||||
#define GPIO45_BTRTS 45 /* BTUART request to send */
|
||||
#define GPIO45_HWRTS 45 /* HWUART request to send */
|
||||
#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
|
||||
#define GPIO46_ICPRXD 46 /* ICP receive data */
|
||||
#define GPIO46_STRXD 46 /* STD_UART receive data */
|
||||
|
|
@ -1378,17 +1399,26 @@
|
|||
#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
|
||||
#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
|
||||
#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
|
||||
#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
|
||||
#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
|
||||
#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
|
||||
#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
|
||||
#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
|
||||
#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
|
||||
#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
|
||||
#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
|
||||
#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
|
||||
|
|
@ -1763,6 +1793,7 @@
|
|||
#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
|
||||
#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
|
||||
#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
|
||||
#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
|
||||
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
|
||||
#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
|
||||
#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
|
||||
|
|
@ -2282,4 +2313,11 @@
|
|||
|
||||
#endif
|
||||
|
||||
/* PWRMODE register M field values */
|
||||
|
||||
#define PWRMODE_IDLE 0x1
|
||||
#define PWRMODE_STANDBY 0x2
|
||||
#define PWRMODE_SLEEP 0x3
|
||||
#define PWRMODE_DEEPSLEEP 0x7
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#define FFUART ((volatile unsigned long *)0x40100000)
|
||||
#define BTUART ((volatile unsigned long *)0x40200000)
|
||||
#define STUART ((volatile unsigned long *)0x40700000)
|
||||
#define HWUART ((volatile unsigned long *)0x41600000)
|
||||
|
||||
#define UART FFUART
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
* 07-Sep-2004 RTP Created file
|
||||
* 03-Nov-2004 BJD Updated and minor cleanups
|
||||
* 03-Aug-2005 RTP Renamed to fb.h
|
||||
* 26-Oct-2005 BJD Changed name of platdata init
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_FB_H
|
||||
|
|
@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
|
|||
unsigned long lpcsel;
|
||||
};
|
||||
|
||||
void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
|
||||
extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
|
||||
|
||||
#endif /* __ASM_ARM_FB_H */
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
* 18-11-2004 BJD Added S3C2440 AC97 controls
|
||||
* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
|
||||
* 28-Mar-2005 LCVR Fixed definition of GPB10
|
||||
* 26-Oct-2005 BJD Added generic configuration types
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -43,6 +44,11 @@
|
|||
/* general configuration options */
|
||||
|
||||
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
|
||||
#define S3C2410_GPIO_INPUT (0xFFFFFFF0)
|
||||
#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
|
||||
#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
|
||||
#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
|
||||
#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
|
||||
|
||||
/* configure GPIO ports A..G */
|
||||
|
||||
|
|
|
|||
|
|
@ -21,13 +21,6 @@
|
|||
#define UNCACHEABLE_ADDR 0xfa050000
|
||||
|
||||
|
||||
/*
|
||||
* We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for
|
||||
* in*()/out*() macros to be usable for all cases.
|
||||
*/
|
||||
#define PCIO_BASE 0
|
||||
|
||||
|
||||
/*
|
||||
* SA1100 internal I/O mappings
|
||||
*
|
||||
|
|
|
|||
|
|
@ -10,13 +10,19 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
* We don't actually have real ISA nor PCI buses, but there is so many
|
||||
* drivers out there that might just work if we fake them...
|
||||
*/
|
||||
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
|
||||
static inline void __iomem *__io(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)addr;
|
||||
}
|
||||
#define __io(a) __io(a)
|
||||
#define __mem_pci(a) (a)
|
||||
#define __mem_isa(a) (a)
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#include <linux/types.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/*
|
||||
* ISA I/O bus memory addresses are 1:1 with the physical address.
|
||||
|
|
|
|||
|
|
@ -48,10 +48,10 @@ struct machine_desc {
|
|||
* Set of macros to define architecture features. This is built into
|
||||
* a table by the linker.
|
||||
*/
|
||||
#define MACHINE_START(_type,_name) \
|
||||
const struct machine_desc __mach_desc_##_type \
|
||||
#define MACHINE_START(_type,_name) \
|
||||
static const struct machine_desc __mach_desc_##_type \
|
||||
__attribute__((__section__(".arch.info.init"))) = { \
|
||||
.nr = MACH_TYPE_##_type, \
|
||||
.nr = MACH_TYPE_##_type, \
|
||||
.name = _name,
|
||||
|
||||
#define MACHINE_END \
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
struct map_desc {
|
||||
unsigned long virtual;
|
||||
unsigned long physical;
|
||||
unsigned long pfn;
|
||||
unsigned long length;
|
||||
unsigned int type;
|
||||
};
|
||||
|
|
@ -27,6 +27,9 @@ struct meminfo;
|
|||
#define MT_ROM 6
|
||||
#define MT_IXP2000_DEVICE 7
|
||||
|
||||
#define __phys_to_pfn(paddr) (paddr >> PAGE_SHIFT)
|
||||
#define __pfn_to_phys(pfn) (pfn << PAGE_SHIFT)
|
||||
|
||||
extern void create_memmap_holes(struct meminfo *);
|
||||
extern void memtable_init(struct meminfo *);
|
||||
extern void iotable_init(struct map_desc *, int);
|
||||
|
|
|
|||
Loading…
Reference in a new issue