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EDAC, sb_edac: Fix logic when computing DIMM sizes on Xeon Phi

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Correct a typo introduced by

  d0cdf90031 ("EDAC, sb_edac: Add Knights Landing (Xeon Phi gen 2) support")

As a result under some configurations DIMMs were not correctly
recognized. Problem affects only Xeon Phi architecture.

Signed-off-by: Hubert Chrzaniuk <[email protected]>
Acked-by: Aristeu Rozanski <[email protected]>
Cc: Mauro Carvalho Chehab <[email protected]>
Cc: linux-edac <[email protected]>
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Borislav Petkov <[email protected]>
This commit is contained in:
Hubert Chrzaniuk 2016-03-07 15:30:45 +01:00 • committed by Borislav Petkov
commit 83bdaad4d9
1 changed files with 1 additions and 1 deletions
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2
drivers/edac/sb_edac.c
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@ -1574,7 +1574,7 @@ static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
if (knl_get_mc_route(target,
mc_route_reg[cha]) == channel
&& participants[channel]) {
&& !participants[channel]) {
participant_count++;
participants[channel] = 1;
break;