From 83d72184f09c8d6d291cc6a600b62943ace4e8a5 Mon Sep 17 00:00:00 2001 From: houdz1 Date: Wed, 13 Jan 2021 16:24:50 +0800 Subject: [PATCH] dsi_phy_v3.0: Get strength offset from dtsi file and set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock and data lanes have a calibration circuitry feature. To offset the drive strength from the calibrated value in an increasing or decreasing manner, use 6 bit two’s complement values. Change-Id: I1cb612b4f62ea6af07165ffd1fb8e15528200e5e Signed-off-by: houdz1 Reviewed-on: https://gerrit.mot.com/1850370 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Yeqing Wang Reviewed-by: Huosheng Liao Submit-Approved: Jira Key --- msm/dsi/dsi_phy.c | 2 +- msm/dsi/dsi_phy_hw_v3_0.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/msm/dsi/dsi_phy.c b/msm/dsi/dsi_phy.c index 3ae158db391e..4aaeabd93c2e 100644 --- a/msm/dsi/dsi_phy.c +++ b/msm/dsi/dsi_phy.c @@ -63,7 +63,7 @@ static const struct dsi_ver_spec_info dsi_phy_v2_0 = { static const struct dsi_ver_spec_info dsi_phy_v3_0 = { .version = DSI_PHY_VERSION_3_0, .lane_cfg_count = 4, - .strength_cfg_count = 2, + .strength_cfg_count = 4, .regulator_cfg_count = 0, .timing_cfg_count = 12, }; diff --git a/msm/dsi/dsi_phy_hw_v3_0.c b/msm/dsi/dsi_phy_hw_v3_0.c index a863827050ad..4b8992bc07c3 100644 --- a/msm/dsi/dsi_phy_hw_v3_0.c +++ b/msm/dsi/dsi_phy_hw_v3_0.c @@ -194,8 +194,8 @@ static void dsi_phy_hw_v3_0_lane_settings(struct dsi_phy_hw *phy, DSI_W32(phy, DSIPHY_LNX_CFG1(i), cfg->lanecfg.lane[i][1]); DSI_W32(phy, DSIPHY_LNX_CFG2(i), cfg->lanecfg.lane[i][2]); DSI_W32(phy, DSIPHY_LNX_CFG3(i), cfg->lanecfg.lane[i][3]); - DSI_W32(phy, DSIPHY_LNX_OFFSET_TOP_CTRL(i), 0x0); - DSI_W32(phy, DSIPHY_LNX_OFFSET_BOT_CTRL(i), 0x0); + DSI_W32(phy, DSIPHY_LNX_OFFSET_TOP_CTRL(i), cfg->strength.lane[i][2]); + DSI_W32(phy, DSIPHY_LNX_OFFSET_BOT_CTRL(i), cfg->strength.lane[i][3]); DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]); } }