mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
Merge 4.13-rc7 into staging-next
We want the staging and iio fixes in here to handle the merge issues. Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Greg Kroah-Hartman
commit
8439a69e72
408 changed files with 2975 additions and 1440 deletions
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@ -666,7 +666,7 @@ static int ina2xx_capture_thread(void *data)
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{
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struct iio_dev *indio_dev = data;
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struct ina2xx_chip_info *chip = iio_priv(indio_dev);
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unsigned int sampling_us = SAMPLING_PERIOD(chip);
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int sampling_us = SAMPLING_PERIOD(chip);
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int buffer_us;
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/*
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@ -64,7 +64,7 @@
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#define STM32H7_CKMODE_MASK GENMASK(17, 16)
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/* STM32 H7 maximum analog clock rate (from datasheet) */
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#define STM32H7_ADC_MAX_CLK_RATE 72000000
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#define STM32H7_ADC_MAX_CLK_RATE 36000000
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/**
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* stm32_adc_common_regs - stm32 common registers, compatible dependent data
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@ -148,14 +148,14 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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return -EINVAL;
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}
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priv->common.rate = rate;
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priv->common.rate = rate / stm32f4_pclk_div[i];
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val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
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val &= ~STM32F4_ADC_ADCPRE_MASK;
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val |= i << STM32F4_ADC_ADCPRE_SHIFT;
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writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
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dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
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rate / (stm32f4_pclk_div[i] * 1000));
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priv->common.rate / 1000);
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return 0;
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}
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@ -250,7 +250,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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out:
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/* rate used later by each ADC instance to control BOOST mode */
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priv->common.rate = rate;
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priv->common.rate = rate / div;
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/* Set common clock mode and prescaler */
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val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
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@ -260,7 +260,7 @@ out:
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writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
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dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
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ckmode ? "bus" : "adc", div, rate / (div * 1000));
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ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
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return 0;
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}
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@ -111,8 +111,6 @@ static int _hid_sensor_power_state(struct hid_sensor_common *st, bool state)
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s32 poll_value = 0;
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if (state) {
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if (!atomic_read(&st->user_requested_state))
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return 0;
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if (sensor_hub_device_open(st->hsdev))
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return -EIO;
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@ -161,6 +159,9 @@ static int _hid_sensor_power_state(struct hid_sensor_common *st, bool state)
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&report_val);
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}
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pr_debug("HID_SENSOR %s set power_state %d report_state %d\n",
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st->pdev->name, state_val, report_val);
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sensor_hub_get_feature(st->hsdev, st->power_state.report_id,
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st->power_state.index,
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sizeof(state_val), &state_val);
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@ -182,6 +183,7 @@ int hid_sensor_power_state(struct hid_sensor_common *st, bool state)
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ret = pm_runtime_get_sync(&st->pdev->dev);
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else {
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pm_runtime_mark_last_busy(&st->pdev->dev);
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pm_runtime_use_autosuspend(&st->pdev->dev);
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ret = pm_runtime_put_autosuspend(&st->pdev->dev);
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}
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if (ret < 0) {
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@ -285,8 +287,6 @@ int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name,
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/* Default to 3 seconds, but can be changed from sysfs */
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pm_runtime_set_autosuspend_delay(&attrb->pdev->dev,
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3000);
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pm_runtime_use_autosuspend(&attrb->pdev->dev);
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return ret;
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error_unreg_trigger:
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iio_trigger_unregister(trig);
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@ -696,7 +696,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.gyro_max_val = IIO_RAD_TO_DEGREE(22500),
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.gyro_max_scale = 450,
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.accel_max_val = IIO_M_S_2_TO_G(12500),
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.accel_max_scale = 5,
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.accel_max_scale = 10,
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},
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[ADIS16485] = {
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.channels = adis16485_channels,
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@ -357,9 +357,7 @@ static const struct st_sensor_settings st_magn_sensors_settings[] = {
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.drdy_irq = {
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.addr = 0x62,
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.mask_int1 = 0x01,
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.addr_ihl = 0x63,
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.mask_ihl = 0x04,
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.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
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.addr_stat_drdy = 0x67,
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},
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.multi_read_bit = false,
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.bootime = 2,
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@ -282,6 +282,11 @@ static int bmp280_read_temp(struct bmp280_data *data,
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}
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adc_temp = be32_to_cpu(tmp) >> 12;
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if (adc_temp == BMP280_TEMP_SKIPPED) {
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/* reading was skipped */
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dev_err(data->dev, "reading temperature skipped\n");
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return -EIO;
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}
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comp_temp = bmp280_compensate_temp(data, adc_temp);
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/*
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@ -317,6 +322,11 @@ static int bmp280_read_press(struct bmp280_data *data,
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}
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adc_press = be32_to_cpu(tmp) >> 12;
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if (adc_press == BMP280_PRESS_SKIPPED) {
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/* reading was skipped */
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dev_err(data->dev, "reading pressure skipped\n");
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return -EIO;
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}
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comp_press = bmp280_compensate_press(data, adc_press);
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*val = comp_press;
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@ -345,6 +355,11 @@ static int bmp280_read_humid(struct bmp280_data *data, int *val, int *val2)
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}
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adc_humidity = be16_to_cpu(tmp);
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if (adc_humidity == BMP280_HUMIDITY_SKIPPED) {
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/* reading was skipped */
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dev_err(data->dev, "reading humidity skipped\n");
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return -EIO;
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}
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comp_humidity = bmp280_compensate_humidity(data, adc_humidity);
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*val = comp_humidity;
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@ -597,14 +612,20 @@ static const struct bmp280_chip_info bmp280_chip_info = {
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static int bme280_chip_config(struct bmp280_data *data)
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{
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int ret = bmp280_chip_config(data);
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int ret;
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u8 osrs = BMP280_OSRS_HUMIDITIY_X(data->oversampling_humid + 1);
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/*
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* Oversampling of humidity must be set before oversampling of
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* temperature/pressure is set to become effective.
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*/
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ret = regmap_update_bits(data->regmap, BMP280_REG_CTRL_HUMIDITY,
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BMP280_OSRS_HUMIDITY_MASK, osrs);
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if (ret < 0)
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return ret;
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return regmap_update_bits(data->regmap, BMP280_REG_CTRL_HUMIDITY,
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BMP280_OSRS_HUMIDITY_MASK, osrs);
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return bmp280_chip_config(data);
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}
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static const struct bmp280_chip_info bme280_chip_info = {
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@ -96,6 +96,11 @@
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#define BME280_CHIP_ID 0x60
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#define BMP280_SOFT_RESET_VAL 0xB6
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/* BMP280 register skipped special values */
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#define BMP280_TEMP_SKIPPED 0x80000
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#define BMP280_PRESS_SKIPPED 0x80000
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#define BMP280_HUMIDITY_SKIPPED 0x8000
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/* Regmap configurations */
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extern const struct regmap_config bmp180_regmap_config;
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extern const struct regmap_config bmp280_regmap_config;
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@ -402,34 +402,32 @@ static int stm32_counter_read_raw(struct iio_dev *indio_dev,
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int *val, int *val2, long mask)
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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u32 dat;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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{
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u32 cnt;
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regmap_read(priv->regmap, TIM_CNT, &cnt);
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*val = cnt;
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regmap_read(priv->regmap, TIM_CNT, &dat);
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*val = dat;
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return IIO_VAL_INT;
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}
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case IIO_CHAN_INFO_SCALE:
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{
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u32 smcr;
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regmap_read(priv->regmap, TIM_SMCR, &smcr);
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smcr &= TIM_SMCR_SMS;
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case IIO_CHAN_INFO_ENABLE:
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regmap_read(priv->regmap, TIM_CR1, &dat);
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*val = (dat & TIM_CR1_CEN) ? 1 : 0;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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regmap_read(priv->regmap, TIM_SMCR, &dat);
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dat &= TIM_SMCR_SMS;
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*val = 1;
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*val2 = 0;
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/* in quadrature case scale = 0.25 */
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if (smcr == 3)
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if (dat == 3)
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*val2 = 2;
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return IIO_VAL_FRACTIONAL_LOG2;
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}
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}
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return -EINVAL;
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}
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@ -439,15 +437,31 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev,
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int val, int val2, long mask)
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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u32 dat;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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regmap_write(priv->regmap, TIM_CNT, val);
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return regmap_write(priv->regmap, TIM_CNT, val);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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/* fixed scale */
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return -EINVAL;
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case IIO_CHAN_INFO_ENABLE:
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if (val) {
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regmap_read(priv->regmap, TIM_CR1, &dat);
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if (!(dat & TIM_CR1_CEN))
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clk_enable(priv->clk);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
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TIM_CR1_CEN);
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} else {
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regmap_read(priv->regmap, TIM_CR1, &dat);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
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0);
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if (dat & TIM_CR1_CEN)
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clk_disable(priv->clk);
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}
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return 0;
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}
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return -EINVAL;
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@ -507,7 +521,7 @@ static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
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regmap_read(priv->regmap, TIM_SMCR, &smcr);
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return smcr == TIM_SMCR_SMS ? 0 : -EINVAL;
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return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
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}
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static const struct iio_enum stm32_trigger_mode_enum = {
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@ -543,9 +557,19 @@ static int stm32_set_enable_mode(struct iio_dev *indio_dev,
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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int sms = stm32_enable_mode2sms(mode);
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u32 val;
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if (sms < 0)
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return sms;
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/*
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* Triggered mode sets CEN bit automatically by hardware. So, first
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* enable counter clock, so it can use it. Keeps it in sync with CEN.
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*/
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if (sms == 6) {
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regmap_read(priv->regmap, TIM_CR1, &val);
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if (!(val & TIM_CR1_CEN))
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clk_enable(priv->clk);
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}
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regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
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@ -607,11 +631,14 @@ static int stm32_get_quadrature_mode(struct iio_dev *indio_dev,
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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u32 smcr;
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int mode;
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regmap_read(priv->regmap, TIM_SMCR, &smcr);
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smcr &= TIM_SMCR_SMS;
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mode = (smcr & TIM_SMCR_SMS) - 1;
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if ((mode < 0) || (mode > ARRAY_SIZE(stm32_quadrature_modes)))
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return -EINVAL;
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return smcr - 1;
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return mode;
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}
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static const struct iio_enum stm32_quadrature_mode_enum = {
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@ -628,13 +655,20 @@ static const char *const stm32_count_direction_states[] = {
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static int stm32_set_count_direction(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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unsigned int mode)
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unsigned int dir)
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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u32 val;
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int mode;
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, mode);
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/* In encoder mode, direction is RO (given by TI1/TI2 signals) */
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regmap_read(priv->regmap, TIM_SMCR, &val);
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mode = (val & TIM_SMCR_SMS) - 1;
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if ((mode >= 0) || (mode < ARRAY_SIZE(stm32_quadrature_modes)))
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return -EBUSY;
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return 0;
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return regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR,
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dir ? TIM_CR1_DIR : 0);
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}
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static int stm32_get_count_direction(struct iio_dev *indio_dev,
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@ -645,7 +679,7 @@ static int stm32_get_count_direction(struct iio_dev *indio_dev,
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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return (cr1 & TIM_CR1_DIR);
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return ((cr1 & TIM_CR1_DIR) ? 1 : 0);
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}
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static const struct iio_enum stm32_count_direction_enum = {
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@ -708,7 +742,9 @@ static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
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static const struct iio_chan_spec stm32_trigger_channel = {
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.type = IIO_COUNT,
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_ENABLE) |
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BIT(IIO_CHAN_INFO_SCALE),
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.ext_info = stm32_trigger_count_info,
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.indexed = 1
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};
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