From 84870f513da692fd326011ac817ae1ceebd25711 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 24 Nov 2020 17:53:15 +0800 Subject: [PATCH] ARM: dts: msm: refine QDSS config for sdxlemur Add reset and flush trigger number for etr and etf. Change-Id: Iec420ee00ac45ca37e525f3736e0204d6c36e71b --- qcom/sdxlemur-coresight.dtsi | 8 ++++++-- qcom/sdxlemur.dtsi | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 2e977b84e52b..073cfa4332f9 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -147,7 +149,9 @@ arm,scatter-gather; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..0553ed188bfc 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -946,6 +946,7 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-regulators.dtsi" +#include "sdxlemur-coresight.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi"