From d3c7cff028bb770d1f728aa1769eee624017635d Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Thu, 1 Apr 2021 14:36:58 +0530 Subject: [PATCH] msm: camera: cpas: Change to set OT value to 8 for RT block This change is set the OT values for RT client of Camonc to 8 for Yupik camera. CRs-Fixed: 2924987 Change-Id: Icb7f30c23f5899558a41308fe313d46fd8d992a3 Signed-off-by: Ayush Kumar --- drivers/cam_cpas/cpas_top/cpastop_v165_100.h | 63 ++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/cam_cpas/cpas_top/cpastop_v165_100.h b/drivers/cam_cpas/cpas_top/cpastop_v165_100.h index 8e41284604f6..9dc47566bb37 100644 --- a/drivers/cam_cpas/cpas_top/cpastop_v165_100.h +++ b/drivers/cam_cpas/cpas_top/cpastop_v165_100.h @@ -289,6 +289,27 @@ static struct cam_camnoc_specific */ .enable = false, }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4808, /* IFE01234_RDI_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4820, /* IFE01234_RDI_QOSGEN_SHAPING_LOW */ + .value = 0x07070707, + }, + .qosgen_shaping_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4824, /* IFE01234_RDI_QOSGEN_SHAPING_HIGH */ + .value = 0x07070707, + }, }, { .port_type = CAM_CAMNOC_IFE01_NRDI_WRITE, @@ -343,6 +364,27 @@ static struct cam_camnoc_specific .offset = 0x3B88, /* IFE01_NRDI_ENCCTL_LOW */ .value = 1, }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4708, /* IFE01_NRDI_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4720, /* IFE01_NRDI_QOSGEN_SHAPING_LOW */ + .value = 0x07070707, + }, + .qosgen_shaping_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4724, /* IFE01_NRDI_QOSGEN_SHAPING_HIGH */ + .value = 0x07070707, + }, }, { .port_type = CAM_CAMNOC_IFE2_NRDI_WRITE, @@ -397,6 +439,27 @@ static struct cam_camnoc_specific .offset = 0x5588, /* IFE2_NRDI_ENCCTL_LOW */ .value = 0, }, + .qosgen_mainctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5188, /* IFE2_NRDI_QOSGEN_MAINCTL */ + .value = 0x2, + }, + .qosgen_shaping_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x51A0, /* IFE2_NRDI_QOSGEN_SHAPING_LOW */ + .value = 0x07070707, + }, + .qosgen_shaping_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x51A4, /* IFE2_NRDI_QOSGEN_SHAPING_HIGH */ + .value = 0x07070707, + }, }, { .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,