A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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qcacmn: Re-configure interrupt bits once again after FW resets

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Issue:
Customer sees a lot of NOC errors after wifi comes up as
FW resets the interrupt bits that host configured and
then checks whether interrupt bits are enabled. FW then enters
into MSI mode without filling the necessary MSI address and MSI
data registers with proper values and this leads to lot
of NOC errors on the platform.

Fix description:
Configure the interrupt bits one more time after FW
resets the registers and then mark the host ready bit
in FW indicator address

CRs-Fixed: 2056198
Change-Id: I7a8871a9878b415ec90c4938df669c6225e79586
This commit is contained in:
c_priys 2018-05-31 12:46:53 +05:30 • committed by nshrivas
commit 85191774b5
1 changed files with 17 additions and 0 deletions
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17
hif/src/snoc/if_ahb.c
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@ -363,6 +363,23 @@ irqreturn_t hif_ahb_interrupt_handler(int irq, void *context)
*/
int hif_target_sync_ahb(struct hif_softc *scn)
{
int val = 0;
int limit = 0;
while (limit < 50) {
hif_write32_mb(scn->mem +
(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS),
PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
qdf_mdelay(10);
val = hif_read32_mb(scn->mem +
(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS));
if (val == 0)
break;
limit++;
}
hif_write32_mb(scn->mem +
(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS),
PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
hif_write32_mb(scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
if (HAS_FW_INDICATOR) {
int wait_limit = 500;