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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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drm next pull request for 5.1
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Merge tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"This is the main drm pull request for the 5.1 merge window.
The big changes I'd highlight are:
- nouveau has HMM support now, there is finally an in-tree user so we
can quieten down the rip it out people.
- i915 now enables fastboot by default on Skylake+
- Displayport Multistream support has been refactored and should
hopefully be more reliable.
Core:
- header cleanups aiming towards removing drmP.h
- dma-buf fence seqnos to 64-bits
- common helper for DP mst hotplug for radeon,i915,amdgpu + new
refcounting scheme
- MST i2c improvements
- drm_syncobj_cb removal
- ARM FB compression fourcc
- P010 + P016 fourcc
- allwinner tiled format modifier
- i2c over aux I2C_M_STOP support
- DRM_AUTH handling fixes
TTM:
- ref/unref renaming
New driver:
- ARM komeda display driver
scheduler:
- refactor mirror list handling
- rework hw fence processing
- 0 run queue entity fix
bridge:
- TI DS90C185 LVDS bridge
- thc631lvdm83d bridge improvements
- cadence + allwinner DSI ported to generic phy
panels:
- Sitronix ST7701 panel
- Kingdisplay KD097D04
- LeMaker BL035-RGB-002
- PDA 91-00156-A0
- Innolux EE101IA-01D
i915:
- Enable fastboot by default on SKL+/VLV/CHV
- Export RPCS configuration for ICL media driver
- Coffelake PCI ID
- CNL clocks setup fixes
- ACPI/PMIC support for MIPI/DSI
- Per-engine WA init for all engines
- Shrinker locking fixes
- Kerneldoc updates
- Lots of ring improvements and reset fixes
- Coffeelake GVT Support
- VFIO GVT EDID Region support
- runtime PM wakeref tracking
- ILK->IVB primary plane enable delays
- userptr mutex locking fixes
- DSI fixes
- LVDS/TV cleanups
- HW readout fixes
- LUT robustness fixes
- ICL display and watermark fixes
- gem mmap race fix
amdgpu:
- add scheduled dependencies interface
- DCC on scanout surfaces
- vega10/20 BACO support
- Multiple IH rings on soc15
- XGMI locking fixes
- DC i2c/aux cleanups
- runtime SMU debug interface
- Kexec improvmeents
- SR-IOV fixes
- DC freesync + ABM fixes
- GDS fixes
- GPUVM fixes
- vega20 PCIE DPM switching fixes
- Context priority handling fixes
radeon:
- fix missing break in evergreen parser
nouveau:
- SVM support via HMM
msm:
- QCOM Compressed modifier support
exynos:
- s5pv210 rotator support
imx:
- zpos property support
- pending update fixes
v3d:
- cache flush improvments
vc4:
- reflection support
- HDMI overscan support
tegra:
- CEC refactoring
- HDMI audio fixes
- Tegra186 prep work
- SOR crossbar device tree fixes
sun4i:
- implicit fencing support
- YUV and scalar support improvements
- A23 support
- tiling fixes
atmel-hlcdc:
- clipping and rotation property fixes
qxl:
- BO and PRIME improvements
- generic fbdev emulation
dw-hdmi:
- HDMI 2.0 2160p
- YUV420 ouput
rockchip:
- implicit fencing support
- reflection proerties
virtio-gpu:
- use generic fbdev emulation
tilcdc:
- cpufreq vs crtc init fix
rcar-du:
- R8A774C0 support
- D3/E3 RGB output routing fixes and DPAD0 support
- RA87744 LVDS support
bochs:
- atomic and generic fbdev emulation
- ID mismatch error on bochs load
meson:
- remove firmware fbs"
* tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm: (1130 commits)
drm/amd/display: Use vrr friendly pageflip throttling in DC.
drm/imx: only send commit done event when all state has been applied
drm/imx: allow building under COMPILE_TEST
drm/imx: imx-tve: depend on COMMON_CLK
drm/imx: ipuv3-plane: add zpos property
drm/imx: ipuv3-plane: add function to query atomic update status
gpu: ipu-v3: prg: add function to get channel configure status
gpu: ipu-v3: pre: add double buffer status readback
drm/amdgpu: Bump amdgpu version for context priority override.
drm/amdgpu/powerplay: fix typo in BACO header guards
drm/amdgpu/powerplay: fix return codes in BACO code
drm/amdgpu: add missing license on baco files
drm/bochs: Fix the ID mismatch error
drm/nouveau/dmem: use dma addresses during migration copies
drm/nouveau/dmem: use physical vram addresses during migration copies
drm/nouveau/dmem: extend copy function to allow direct use of physical addresses
drm/nouveau/svm: new ioctl to migrate process memory to GPU memory
drm/nouveau/dmem: device memory helpers for SVM
drm/nouveau/svm: initial support for shared virtual memory
drm/nouveau: prepare for enabling svm with existing userspace interfaces
...
This commit is contained in:
Linus Torvalds
commit
851ca779d1
1141 changed files with 39562 additions and 37911 deletions
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@ -272,13 +272,14 @@ union drm_amdgpu_vm {
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/* sched ioctl */
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#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
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#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
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struct drm_amdgpu_sched_in {
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/* AMDGPU_SCHED_OP_* */
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__u32 op;
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__u32 fd;
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__s32 priority;
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__u32 flags;
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__u32 ctx_id;
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};
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union drm_amdgpu_sched {
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@ -523,6 +524,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
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#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
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#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
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#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
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struct drm_amdgpu_cs_chunk {
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__u32 chunk_id;
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@ -565,6 +567,11 @@ union drm_amdgpu_cs {
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* caches (L2/vL1/sL1/I$). */
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#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
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/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
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* This will reset wave ID counters for the IB.
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*/
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#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
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struct drm_amdgpu_cs_chunk_ib {
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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@ -195,6 +195,27 @@ extern "C" {
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#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [10:6] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
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*/
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#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [12:4] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
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*/
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#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
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*/
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#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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@ -238,6 +259,8 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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/* add more to the end as needed */
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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@ -572,6 +595,9 @@ extern "C" {
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* AFBC has several features which may be supported and/or used, which are
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* represented using bits in the modifier. Not all combinations are valid,
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* and different devices or use-cases may support different combinations.
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*
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* Further information on the use of AFBC modifiers can be found in
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* Documentation/gpu/afbc.rst
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*/
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#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
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@ -581,10 +607,18 @@ extern "C" {
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* Indicates the superblock size(s) used for the AFBC buffer. The buffer
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* size (in pixels) must be aligned to a multiple of the superblock size.
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* Four lowest significant bits(LSBs) are reserved for block size.
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*
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* Where one superblock size is specified, it applies to all planes of the
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* buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
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* the first applies to the Luma plane and the second applies to the Chroma
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* plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
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* Multiple superblock sizes are only valid for multi-plane YCbCr formats.
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*/
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
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/*
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* AFBC lossless colorspace transform
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@ -644,6 +678,35 @@ extern "C" {
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*/
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#define AFBC_FORMAT_MOD_SC (1ULL << 9)
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/*
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* AFBC double-buffer
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*
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* Indicates that the buffer is allocated in a layout safe for front-buffer
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* rendering.
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*/
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#define AFBC_FORMAT_MOD_DB (1ULL << 10)
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/*
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* AFBC buffer content hints
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*
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* Indicates that the buffer includes per-superblock content hints.
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*/
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#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
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/*
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* Allwinner tiled modifier
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*
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* This tiling mode is implemented by the VPU found on all Allwinner platforms,
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* codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
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* planes.
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*
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* With this tiling, the luminance samples are disposed in tiles representing
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* 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
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* The pixel order in each tile is linear and the tiles are disposed linearly,
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* both in row-major order.
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*/
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#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
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#if defined(__cplusplus)
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}
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#endif
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@ -1486,9 +1486,73 @@ struct drm_i915_gem_context_param {
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#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
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#define I915_CONTEXT_DEFAULT_PRIORITY 0
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#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
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/*
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* When using the following param, value should be a pointer to
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* drm_i915_gem_context_param_sseu.
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*/
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#define I915_CONTEXT_PARAM_SSEU 0x7
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__u64 value;
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};
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/**
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* Context SSEU programming
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*
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* It may be necessary for either functional or performance reason to configure
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* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
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* Sub-slice/EU).
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*
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* This is done by configuring SSEU configuration using the below
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* @struct drm_i915_gem_context_param_sseu for every supported engine which
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* userspace intends to use.
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*
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* Not all GPUs or engines support this functionality in which case an error
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* code -ENODEV will be returned.
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*
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* Also, flexibility of possible SSEU configuration permutations varies between
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* GPU generations and software imposed limitations. Requesting such a
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* combination will return an error code of -EINVAL.
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*
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* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
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* favour of a single global setting.
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*/
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struct drm_i915_gem_context_param_sseu {
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/*
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* Engine class & instance to be configured or queried.
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*/
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__u16 engine_class;
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__u16 engine_instance;
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/*
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* Unused for now. Must be cleared to zero.
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*/
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__u32 flags;
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/*
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* Mask of slices to enable for the context. Valid values are a subset
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* of the bitmask value returned for I915_PARAM_SLICE_MASK.
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*/
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__u64 slice_mask;
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/*
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* Mask of subslices to enable for the context. Valid values are a
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* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
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*/
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__u64 subslice_mask;
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/*
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* Minimum/Maximum number of EUs to enable per subslice for the
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* context. min_eus_per_subslice must be inferior or equal to
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* max_eus_per_subslice.
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*/
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__u16 min_eus_per_subslice;
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__u16 max_eus_per_subslice;
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/*
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* Unused for now. Must be cleared to zero.
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*/
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__u32 rsvd;
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};
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enum drm_i915_oa_format {
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I915_OA_FORMAT_A13 = 1, /* HSW only */
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I915_OA_FORMAT_A29, /* HSW only */
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@ -133,12 +133,63 @@ struct drm_nouveau_gem_cpu_fini {
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#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
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#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
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#define DRM_NOUVEAU_NVIF 0x07
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#define DRM_NOUVEAU_SVM_INIT 0x08
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#define DRM_NOUVEAU_SVM_BIND 0x09
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#define DRM_NOUVEAU_GEM_NEW 0x40
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#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
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#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
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#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
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#define DRM_NOUVEAU_GEM_INFO 0x44
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struct drm_nouveau_svm_init {
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__u64 unmanaged_addr;
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__u64 unmanaged_size;
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};
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struct drm_nouveau_svm_bind {
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__u64 header;
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__u64 va_start;
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__u64 va_end;
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__u64 npages;
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__u64 stride;
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__u64 result;
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__u64 reserved0;
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__u64 reserved1;
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};
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#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
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#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
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#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
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#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
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#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
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#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
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#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
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#define NOUVEAU_SVM_BIND_TARGET_BITS 32
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#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
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/*
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* Below is use to validate ioctl argument, userspace can also use it to make
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* sure that no bit are set beyond known fields for a given kernel version.
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*/
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#define NOUVEAU_SVM_BIND_VALID_BITS 48
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#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
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/*
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* NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
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* result: number of page successfuly migrate to the target memory.
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*/
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#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
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/*
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* NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
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*/
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#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
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#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
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#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
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#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
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#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
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#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
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|
|
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|||
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|
@ -52,6 +52,14 @@ extern "C" {
|
|||
*
|
||||
* This asks the kernel to have the GPU execute an optional binner
|
||||
* command list, and a render command list.
|
||||
*
|
||||
* The L1T, slice, L2C, L2T, and GCA caches will be flushed before
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* each CL executes. The VCD cache should be flushed (if necessary)
|
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* by the submitted CLs. The TLB writes are guaranteed to have been
|
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* flushed by the time the render done IRQ happens, which is the
|
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* trigger for out_sync. Any dirtying of cachelines by the job (only
|
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* possible using TMU writes) must be flushed by the caller using the
|
||||
* CL's cache flush commands.
|
||||
*/
|
||||
struct drm_v3d_submit_cl {
|
||||
/* Pointer to the binner command list.
|
||||
|
|
|
|||
Loading…
Reference in a new issue