From 85247000b1164aaa9bc4a70a41b2c50a0da657a8 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 15 Jul 2020 12:01:28 +0530 Subject: [PATCH] clk: qcom: gcc-shima: Update video_axi clks to clk_branch2_force_off_ops SMMU fault is observed due to spurious AXI transaction even after gcc video_axi clocks are disabled. HW underlying may not actually turn off clocks since HW enable signals can still be asserted/waiting on certain scenarios like when CVP and MVP both are power collapsed. Use clk_branch2_force_off_ops to guarantee that clocks are actually turned off when SW disables them. Change-Id: Iaa9250a5962f3e74e971b4fc859d246960f792b0 Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/gcc-shima.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-shima.c b/drivers/clk/qcom/gcc-shima.c index c174036a88b7..768eb1662ef7 100644 --- a/drivers/clk/qcom/gcc-shima.c +++ b/drivers/clk/qcom/gcc-shima.c @@ -3184,7 +3184,7 @@ static struct clk_branch gcc_video_axi0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_force_off_ops, }, }, }; @@ -3199,7 +3199,7 @@ static struct clk_branch gcc_video_axi1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_force_off_ops, }, }, };