mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
qcacmn: Move hif_set_hia to pci file
hif_set_hia isn't applicable to non pci targets. Avoid needing a dummy hif_wake_target_cpu for snoc. Change-Id: I1ebdac2f1ea1c87466ba144986ff151f074476ba CRs-Fixed: 986480
This commit is contained in:
Houston Hoffman
Vishwajith Upendra
parent
f771862053
commit
854e67f791
4 changed files with 354 additions and 298 deletions
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@ -1499,31 +1499,6 @@ static struct service_to_pipe target_service_to_ce_map_wlan_epping[] = {
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{0, 0, 0,}, /* Must be last */
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};
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#ifdef HIF_PCI
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/*
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* Send an interrupt to the device to wake up the Target CPU
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* so it has an opportunity to notice any changed state.
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*/
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void hif_wake_target_cpu(struct hif_softc *scn)
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{
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QDF_STATUS rv;
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uint32_t core_ctrl;
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struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn);
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rv = hif_diag_read_access(hif_hdl,
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SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS,
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&core_ctrl);
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QDF_ASSERT(rv == QDF_STATUS_SUCCESS);
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/* A_INUM_FIRMWARE interrupt to Target CPU */
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core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
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rv = hif_diag_write_access(hif_hdl,
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SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS,
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core_ctrl);
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QDF_ASSERT(rv == QDF_STATUS_SUCCESS);
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}
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#endif
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static void hif_sleep_entry(void *arg)
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{
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struct HIF_CE_state *hif_state = (struct HIF_CE_state *)arg;
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@ -1557,272 +1532,41 @@ static void hif_sleep_entry(void *arg)
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}
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qdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock);
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}
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#define HIF_HIA_MAX_POLL_LOOP 1000000
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#define HIF_HIA_POLLING_DELAY_MS 10
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#ifndef HIF_PCI
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int hif_set_hia(struct hif_softc *scn)
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/**
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* hif_get_target_ce_config() - get copy engine configuration
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* @target_ce_config_ret: basic copy engine configuration
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* @target_ce_config_sz_ret: size of the basic configuration in bytes
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* @target_service_to_ce_map_ret: service mapping for the copy engines
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* @target_service_to_ce_map_sz_ret: size of the mapping in bytes
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* @target_shadow_reg_cfg_ret: shadow register configuration
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* @shadow_cfg_sz_ret: size of the shadow register configuration in bytes
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*
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* providing accessor to these values outside of this file.
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* currently these are stored in static pointers to const sections.
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* there are multiple configurations that are selected from at compile time.
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* Runtime selection would need to consider mode, target type and bus type.
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*
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* Return: return by parameter.
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*/
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void hif_get_target_ce_config(struct CE_pipe_config **target_ce_config_ret,
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int *target_ce_config_sz_ret,
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struct service_to_pipe **target_service_to_ce_map_ret,
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int *target_service_to_ce_map_sz_ret,
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struct shadow_reg_cfg **target_shadow_reg_cfg_ret,
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int *shadow_cfg_sz_ret)
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{
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return 0;
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*target_ce_config_ret = target_ce_config;
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*target_ce_config_sz_ret = target_ce_config_sz;
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*target_service_to_ce_map_ret = target_service_to_ce_map;
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*target_service_to_ce_map_sz_ret = target_service_to_ce_map_sz;
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if (target_shadow_reg_cfg_ret)
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*target_shadow_reg_cfg_ret = target_shadow_reg_cfg;
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if (shadow_cfg_sz_ret)
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*shadow_cfg_sz_ret = shadow_cfg_sz;
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}
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#else
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int hif_set_hia(struct hif_softc *scn)
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{
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QDF_STATUS rv;
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uint32_t interconnect_targ_addr = 0;
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uint32_t pcie_state_targ_addr = 0;
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uint32_t pipe_cfg_targ_addr = 0;
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uint32_t svc_to_pipe_map = 0;
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uint32_t pcie_config_flags = 0;
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uint32_t flag2_value = 0;
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uint32_t flag2_targ_addr = 0;
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#ifdef QCA_WIFI_3_0
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uint32_t host_interest_area = 0;
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uint8_t i;
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#else
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uint32_t ealloc_value = 0;
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uint32_t ealloc_targ_addr = 0;
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uint8_t banks_switched = 1;
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uint32_t chip_id;
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#endif
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uint32_t pipe_cfg_addr;
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struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn);
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struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl);
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uint32_t target_type = tgt_info->target_type;
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HIF_TRACE("%s: E", __func__);
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if (ADRASTEA_BU)
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return QDF_STATUS_SUCCESS;
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#ifdef QCA_WIFI_3_0
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i = 0;
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while (i < HIF_HIA_MAX_POLL_LOOP) {
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host_interest_area = hif_read32_mb(scn->mem +
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A_SOC_CORE_SCRATCH_0_ADDRESS);
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if ((host_interest_area & 0x01) == 0) {
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qdf_mdelay(HIF_HIA_POLLING_DELAY_MS);
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host_interest_area = 0;
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i++;
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if (i > HIF_HIA_MAX_POLL_LOOP && (i % 1000 == 0)) {
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HIF_ERROR("%s: poll timeout(%d)", __func__, i);
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}
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} else {
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host_interest_area &= (~0x01);
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hif_write32_mb(scn->mem + 0x113014, 0);
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break;
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}
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}
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if (i >= HIF_HIA_MAX_POLL_LOOP) {
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HIF_ERROR("%s: hia polling timeout", __func__);
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return -EIO;
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}
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if (host_interest_area == 0) {
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HIF_ERROR("%s: host_interest_area = 0", __func__);
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return -EIO;
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}
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interconnect_targ_addr = host_interest_area +
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offsetof(struct host_interest_area_t,
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hi_interconnect_state);
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flag2_targ_addr = host_interest_area +
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offsetof(struct host_interest_area_t, hi_option_flag2);
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#else
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interconnect_targ_addr = hif_hia_item_address(target_type,
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offsetof(struct host_interest_s, hi_interconnect_state));
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ealloc_targ_addr = hif_hia_item_address(target_type,
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offsetof(struct host_interest_s, hi_early_alloc));
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flag2_targ_addr = hif_hia_item_address(target_type,
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offsetof(struct host_interest_s, hi_option_flag2));
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#endif
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/* Supply Target-side CE configuration */
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rv = hif_diag_read_access(hif_hdl, interconnect_targ_addr,
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&pcie_state_targ_addr);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: interconnect_targ_addr = 0x%0x, ret = %d",
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__func__, interconnect_targ_addr, rv);
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goto done;
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}
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if (pcie_state_targ_addr == 0) {
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rv = QDF_STATUS_E_FAILURE;
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HIF_ERROR("%s: pcie state addr is 0", __func__);
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goto done;
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}
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pipe_cfg_addr = pcie_state_targ_addr +
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offsetof(struct pcie_state_s,
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pipe_cfg_addr);
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rv = hif_diag_read_access(hif_hdl,
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pipe_cfg_addr,
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&pipe_cfg_targ_addr);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: pipe_cfg_addr = 0x%0x, ret = %d",
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__func__, pipe_cfg_addr, rv);
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goto done;
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}
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if (pipe_cfg_targ_addr == 0) {
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rv = QDF_STATUS_E_FAILURE;
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HIF_ERROR("%s: pipe cfg addr is 0", __func__);
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goto done;
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}
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rv = hif_diag_write_mem(hif_hdl, pipe_cfg_targ_addr,
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(uint8_t *) target_ce_config,
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target_ce_config_sz);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: write pipe cfg (%d)", __func__, rv);
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goto done;
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}
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rv = hif_diag_read_access(hif_hdl,
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pcie_state_targ_addr +
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offsetof(struct pcie_state_s,
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svc_to_pipe_map),
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&svc_to_pipe_map);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: get svc/pipe map (%d)", __func__, rv);
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goto done;
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}
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if (svc_to_pipe_map == 0) {
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rv = QDF_STATUS_E_FAILURE;
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HIF_ERROR("%s: svc_to_pipe map is 0", __func__);
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goto done;
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}
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rv = hif_diag_write_mem(hif_hdl,
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svc_to_pipe_map,
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(uint8_t *) target_service_to_ce_map,
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target_service_to_ce_map_sz);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: write svc/pipe map (%d)", __func__, rv);
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goto done;
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}
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rv = hif_diag_read_access(hif_hdl,
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pcie_state_targ_addr +
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offsetof(struct pcie_state_s,
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config_flags),
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&pcie_config_flags);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: get pcie config_flags (%d)", __func__, rv);
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goto done;
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}
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#if (CONFIG_PCIE_ENABLE_L1_CLOCK_GATE)
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pcie_config_flags |= PCIE_CONFIG_FLAG_ENABLE_L1;
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#else
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pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
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#endif /* CONFIG_PCIE_ENABLE_L1_CLOCK_GATE */
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pcie_config_flags |= PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT;
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#if (CONFIG_PCIE_ENABLE_AXI_CLK_GATE)
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pcie_config_flags |= PCIE_CONFIG_FLAG_AXI_CLK_GATE;
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#endif
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rv = hif_diag_write_mem(hif_hdl,
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pcie_state_targ_addr +
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offsetof(struct pcie_state_s,
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config_flags),
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(uint8_t *) &pcie_config_flags,
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sizeof(pcie_config_flags));
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: write pcie config_flags (%d)", __func__, rv);
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goto done;
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}
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#ifndef QCA_WIFI_3_0
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/* configure early allocation */
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ealloc_targ_addr = hif_hia_item_address(target_type,
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offsetof(
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struct host_interest_s,
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hi_early_alloc));
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rv = hif_diag_read_access(hif_hdl, ealloc_targ_addr,
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&ealloc_value);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: get early alloc val (%d)", __func__, rv);
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goto done;
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}
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/* 1 bank is switched to IRAM, except ROME 1.0 */
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ealloc_value |=
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((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
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HI_EARLY_ALLOC_MAGIC_MASK);
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rv = hif_diag_read_access(hif_hdl,
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CHIP_ID_ADDRESS |
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RTC_SOC_BASE_ADDRESS, &chip_id);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: get chip id val (%d)", __func__, rv);
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goto done;
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}
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if (CHIP_ID_VERSION_GET(chip_id) == 0xD) {
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tgt_info->target_revision = CHIP_ID_REVISION_GET(chip_id);
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switch (CHIP_ID_REVISION_GET(chip_id)) {
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case 0x2: /* ROME 1.3 */
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/* 2 banks are switched to IRAM */
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banks_switched = 2;
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break;
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case 0x4: /* ROME 2.1 */
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case 0x5: /* ROME 2.2 */
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banks_switched = 6;
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break;
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case 0x8: /* ROME 3.0 */
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case 0x9: /* ROME 3.1 */
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case 0xA: /* ROME 3.2 */
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banks_switched = 9;
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break;
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case 0x0: /* ROME 1.0 */
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case 0x1: /* ROME 1.1 */
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default:
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/* 3 banks are switched to IRAM */
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banks_switched = 3;
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break;
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}
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}
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ealloc_value |=
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((banks_switched << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
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& HI_EARLY_ALLOC_IRAM_BANKS_MASK);
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rv = hif_diag_write_access(hif_hdl,
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ealloc_targ_addr,
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ealloc_value);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: set early alloc val (%d)", __func__, rv);
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goto done;
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}
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#endif
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/* Tell Target to proceed with initialization */
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flag2_targ_addr = hif_hia_item_address(target_type,
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offsetof(
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struct host_interest_s,
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hi_option_flag2));
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rv = hif_diag_read_access(hif_hdl, flag2_targ_addr,
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&flag2_value);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: get option val (%d)", __func__, rv);
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goto done;
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}
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flag2_value |= HI_OPTION_EARLY_CFG_DONE;
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rv = hif_diag_write_access(hif_hdl, flag2_targ_addr,
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flag2_value);
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if (rv != QDF_STATUS_SUCCESS) {
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HIF_ERROR("%s: set option val (%d)", __func__, rv);
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goto done;
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}
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hif_wake_target_cpu(scn);
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done:
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return rv;
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}
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#endif
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/**
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* hif_wlan_enable(): call the platform driver to enable wlan
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@ -1839,15 +1583,17 @@ int hif_wlan_enable(struct hif_softc *scn)
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enum icnss_driver_mode mode;
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uint32_t con_mode = hif_get_conparam(scn);
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cfg.num_ce_tgt_cfg = target_ce_config_sz /
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sizeof(struct CE_pipe_config);
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cfg.ce_tgt_cfg = (struct ce_tgt_pipe_cfg *)target_ce_config;
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cfg.num_ce_svc_pipe_cfg = target_service_to_ce_map_sz /
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sizeof(struct service_to_pipe);
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cfg.ce_svc_cfg = (struct ce_svc_pipe_cfg *)target_service_to_ce_map;
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cfg.num_shadow_reg_cfg = shadow_cfg_sz / sizeof(struct shadow_reg_cfg);
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cfg.shadow_reg_cfg =
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(struct icnss_shadow_reg_cfg *) target_shadow_reg_cfg;
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hif_get_target_ce_config((struct CE_pipe_config **)&cfg.ce_tgt_cfg,
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&cfg.num_ce_tgt_cfg,
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(struct service_to_pipe **)&cfg.ce_svc_cfg,
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&cfg.num_ce_svc_pipe_cfg,
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(struct shadow_reg_cfg **)&cfg.shadow_reg_cfg,
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&cfg.num_shadow_reg_cfg);
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/* translate from structure size to array size */
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cfg.num_ce_tgt_cfg /= sizeof(struct CE_pipe_config);
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cfg.num_ce_svc_pipe_cfg /= sizeof(struct service_to_pipe);
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cfg.num_shadow_reg_cfg /= sizeof(struct shadow_reg_cfg);
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if (QDF_GLOBAL_FTM_MODE == con_mode)
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mode = ICNSS_FTM;
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@ -133,4 +133,13 @@ struct HIF_CE_state {
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struct CE_handle *ce_diag;
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};
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int hif_dump_ce_registers(struct hif_softc *scn);
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int hif_wlan_enable(struct hif_softc *scn);
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void hif_wlan_disable(struct hif_softc *scn);
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void hif_get_target_ce_config(struct CE_pipe_config **target_ce_config_ret,
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int *target_ce_config_sz_ret,
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struct service_to_pipe **target_service_to_ce_map_ret,
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int *target_service_to_ce_map_sz_ret,
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struct shadow_reg_cfg **target_shadow_reg_cfg_ret,
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int *shadow_cfg_sz_ret);
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#endif /* __CE_H__ */
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|
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@ -159,11 +159,8 @@ int hif_bus_configure(struct hif_softc *scn);
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int hif_config_ce(struct hif_softc *scn);
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void hif_unconfig_ce(struct hif_softc *scn);
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void hif_ce_prepare_config(struct hif_softc *scn);
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int hif_set_hia(struct hif_softc *scn);
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QDF_STATUS hif_ce_open(struct hif_softc *scn);
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void hif_ce_close(struct hif_softc *scn);
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int hif_wlan_enable(struct hif_softc *scn);
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void hif_wlan_disable(struct hif_softc *scn);
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int athdiag_procfs_init(void *scn);
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void athdiag_procfs_remove(void);
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/* routine to modify the initial buffer count to be allocated on an os
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|
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|
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@ -1239,6 +1239,310 @@ static void hif_register_bmi_callbacks(struct hif_softc *hif_sc)
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}
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}
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/**
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* hif_wake_target_cpu() - wake the target's cpu
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* @scn: hif context
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*
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* Send an interrupt to the device to wake up the Target CPU
|
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* so it has an opportunity to notice any changed state.
|
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*/
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void hif_wake_target_cpu(struct hif_softc *scn)
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{
|
||||
QDF_STATUS rv;
|
||||
uint32_t core_ctrl;
|
||||
struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn);
|
||||
|
||||
rv = hif_diag_read_access(hif_hdl,
|
||||
SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS,
|
||||
&core_ctrl);
|
||||
QDF_ASSERT(rv == QDF_STATUS_SUCCESS);
|
||||
/* A_INUM_FIRMWARE interrupt to Target CPU */
|
||||
core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
|
||||
|
||||
rv = hif_diag_write_access(hif_hdl,
|
||||
SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS,
|
||||
core_ctrl);
|
||||
QDF_ASSERT(rv == QDF_STATUS_SUCCESS);
|
||||
}
|
||||
|
||||
#define HIF_HIA_MAX_POLL_LOOP 1000000
|
||||
#define HIF_HIA_POLLING_DELAY_MS 10
|
||||
|
||||
/**
|
||||
* hif_set_hia() - fill out the host interest area
|
||||
* @scn: hif context
|
||||
*
|
||||
* This is replaced by hif_wlan_enable for integrated targets.
|
||||
* This fills out the host interest area. The firmware will
|
||||
* process these memory addresses when it is first brought out
|
||||
* of reset.
|
||||
*
|
||||
* Return: 0 for success.
|
||||
*/
|
||||
int hif_set_hia(struct hif_softc *scn)
|
||||
{
|
||||
QDF_STATUS rv;
|
||||
uint32_t interconnect_targ_addr = 0;
|
||||
uint32_t pcie_state_targ_addr = 0;
|
||||
uint32_t pipe_cfg_targ_addr = 0;
|
||||
uint32_t svc_to_pipe_map = 0;
|
||||
uint32_t pcie_config_flags = 0;
|
||||
uint32_t flag2_value = 0;
|
||||
uint32_t flag2_targ_addr = 0;
|
||||
#ifdef QCA_WIFI_3_0
|
||||
uint32_t host_interest_area = 0;
|
||||
uint8_t i;
|
||||
#else
|
||||
uint32_t ealloc_value = 0;
|
||||
uint32_t ealloc_targ_addr = 0;
|
||||
uint8_t banks_switched = 1;
|
||||
uint32_t chip_id;
|
||||
#endif
|
||||
uint32_t pipe_cfg_addr;
|
||||
struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn);
|
||||
struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl);
|
||||
uint32_t target_type = tgt_info->target_type;
|
||||
int target_ce_config_sz, target_service_to_ce_map_sz;
|
||||
static struct CE_pipe_config *target_ce_config;
|
||||
struct service_to_pipe *target_service_to_ce_map;
|
||||
|
||||
HIF_TRACE("%s: E", __func__);
|
||||
|
||||
hif_get_target_ce_config(&target_ce_config, &target_ce_config_sz,
|
||||
&target_service_to_ce_map,
|
||||
&target_service_to_ce_map_sz,
|
||||
NULL, NULL);
|
||||
|
||||
if (ADRASTEA_BU)
|
||||
return QDF_STATUS_SUCCESS;
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
i = 0;
|
||||
while (i < HIF_HIA_MAX_POLL_LOOP) {
|
||||
host_interest_area = hif_read32_mb(scn->mem +
|
||||
A_SOC_CORE_SCRATCH_0_ADDRESS);
|
||||
if ((host_interest_area & 0x01) == 0) {
|
||||
qdf_mdelay(HIF_HIA_POLLING_DELAY_MS);
|
||||
host_interest_area = 0;
|
||||
i++;
|
||||
if (i > HIF_HIA_MAX_POLL_LOOP && (i % 1000 == 0))
|
||||
HIF_ERROR("%s: poll timeout(%d)", __func__, i);
|
||||
} else {
|
||||
host_interest_area &= (~0x01);
|
||||
hif_write32_mb(scn->mem + 0x113014, 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i >= HIF_HIA_MAX_POLL_LOOP) {
|
||||
HIF_ERROR("%s: hia polling timeout", __func__);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (host_interest_area == 0) {
|
||||
HIF_ERROR("%s: host_interest_area = 0", __func__);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
interconnect_targ_addr = host_interest_area +
|
||||
offsetof(struct host_interest_area_t,
|
||||
hi_interconnect_state);
|
||||
|
||||
flag2_targ_addr = host_interest_area +
|
||||
offsetof(struct host_interest_area_t, hi_option_flag2);
|
||||
|
||||
#else
|
||||
interconnect_targ_addr = hif_hia_item_address(target_type,
|
||||
offsetof(struct host_interest_s, hi_interconnect_state));
|
||||
ealloc_targ_addr = hif_hia_item_address(target_type,
|
||||
offsetof(struct host_interest_s, hi_early_alloc));
|
||||
flag2_targ_addr = hif_hia_item_address(target_type,
|
||||
offsetof(struct host_interest_s, hi_option_flag2));
|
||||
#endif
|
||||
/* Supply Target-side CE configuration */
|
||||
rv = hif_diag_read_access(hif_hdl, interconnect_targ_addr,
|
||||
&pcie_state_targ_addr);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: interconnect_targ_addr = 0x%0x, ret = %d",
|
||||
__func__, interconnect_targ_addr, rv);
|
||||
goto done;
|
||||
}
|
||||
if (pcie_state_targ_addr == 0) {
|
||||
rv = QDF_STATUS_E_FAILURE;
|
||||
HIF_ERROR("%s: pcie state addr is 0", __func__);
|
||||
goto done;
|
||||
}
|
||||
pipe_cfg_addr = pcie_state_targ_addr +
|
||||
offsetof(struct pcie_state_s,
|
||||
pipe_cfg_addr);
|
||||
rv = hif_diag_read_access(hif_hdl,
|
||||
pipe_cfg_addr,
|
||||
&pipe_cfg_targ_addr);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: pipe_cfg_addr = 0x%0x, ret = %d",
|
||||
__func__, pipe_cfg_addr, rv);
|
||||
goto done;
|
||||
}
|
||||
if (pipe_cfg_targ_addr == 0) {
|
||||
rv = QDF_STATUS_E_FAILURE;
|
||||
HIF_ERROR("%s: pipe cfg addr is 0", __func__);
|
||||
goto done;
|
||||
}
|
||||
|
||||
rv = hif_diag_write_mem(hif_hdl, pipe_cfg_targ_addr,
|
||||
(uint8_t *) target_ce_config,
|
||||
target_ce_config_sz);
|
||||
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: write pipe cfg (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
|
||||
rv = hif_diag_read_access(hif_hdl,
|
||||
pcie_state_targ_addr +
|
||||
offsetof(struct pcie_state_s,
|
||||
svc_to_pipe_map),
|
||||
&svc_to_pipe_map);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: get svc/pipe map (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
if (svc_to_pipe_map == 0) {
|
||||
rv = QDF_STATUS_E_FAILURE;
|
||||
HIF_ERROR("%s: svc_to_pipe map is 0", __func__);
|
||||
goto done;
|
||||
}
|
||||
|
||||
rv = hif_diag_write_mem(hif_hdl,
|
||||
svc_to_pipe_map,
|
||||
(uint8_t *) target_service_to_ce_map,
|
||||
target_service_to_ce_map_sz);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: write svc/pipe map (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
|
||||
rv = hif_diag_read_access(hif_hdl,
|
||||
pcie_state_targ_addr +
|
||||
offsetof(struct pcie_state_s,
|
||||
config_flags),
|
||||
&pcie_config_flags);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: get pcie config_flags (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
#if (CONFIG_PCIE_ENABLE_L1_CLOCK_GATE)
|
||||
pcie_config_flags |= PCIE_CONFIG_FLAG_ENABLE_L1;
|
||||
#else
|
||||
pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
|
||||
#endif /* CONFIG_PCIE_ENABLE_L1_CLOCK_GATE */
|
||||
pcie_config_flags |= PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT;
|
||||
#if (CONFIG_PCIE_ENABLE_AXI_CLK_GATE)
|
||||
pcie_config_flags |= PCIE_CONFIG_FLAG_AXI_CLK_GATE;
|
||||
#endif
|
||||
rv = hif_diag_write_mem(hif_hdl,
|
||||
pcie_state_targ_addr +
|
||||
offsetof(struct pcie_state_s,
|
||||
config_flags),
|
||||
(uint8_t *) &pcie_config_flags,
|
||||
sizeof(pcie_config_flags));
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: write pcie config_flags (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
|
||||
#ifndef QCA_WIFI_3_0
|
||||
/* configure early allocation */
|
||||
ealloc_targ_addr = hif_hia_item_address(target_type,
|
||||
offsetof(
|
||||
struct host_interest_s,
|
||||
hi_early_alloc));
|
||||
|
||||
rv = hif_diag_read_access(hif_hdl, ealloc_targ_addr,
|
||||
&ealloc_value);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: get early alloc val (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* 1 bank is switched to IRAM, except ROME 1.0 */
|
||||
ealloc_value |=
|
||||
((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
|
||||
HI_EARLY_ALLOC_MAGIC_MASK);
|
||||
|
||||
rv = hif_diag_read_access(hif_hdl,
|
||||
CHIP_ID_ADDRESS |
|
||||
RTC_SOC_BASE_ADDRESS, &chip_id);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: get chip id val (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
if (CHIP_ID_VERSION_GET(chip_id) == 0xD) {
|
||||
tgt_info->target_revision = CHIP_ID_REVISION_GET(chip_id);
|
||||
switch (CHIP_ID_REVISION_GET(chip_id)) {
|
||||
case 0x2: /* ROME 1.3 */
|
||||
/* 2 banks are switched to IRAM */
|
||||
banks_switched = 2;
|
||||
break;
|
||||
case 0x4: /* ROME 2.1 */
|
||||
case 0x5: /* ROME 2.2 */
|
||||
banks_switched = 6;
|
||||
break;
|
||||
case 0x8: /* ROME 3.0 */
|
||||
case 0x9: /* ROME 3.1 */
|
||||
case 0xA: /* ROME 3.2 */
|
||||
banks_switched = 9;
|
||||
break;
|
||||
case 0x0: /* ROME 1.0 */
|
||||
case 0x1: /* ROME 1.1 */
|
||||
default:
|
||||
/* 3 banks are switched to IRAM */
|
||||
banks_switched = 3;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ealloc_value |=
|
||||
((banks_switched << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
|
||||
& HI_EARLY_ALLOC_IRAM_BANKS_MASK);
|
||||
|
||||
rv = hif_diag_write_access(hif_hdl,
|
||||
ealloc_targ_addr,
|
||||
ealloc_value);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: set early alloc val (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Tell Target to proceed with initialization */
|
||||
flag2_targ_addr = hif_hia_item_address(target_type,
|
||||
offsetof(
|
||||
struct host_interest_s,
|
||||
hi_option_flag2));
|
||||
|
||||
rv = hif_diag_read_access(hif_hdl, flag2_targ_addr,
|
||||
&flag2_value);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: get option val (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
|
||||
flag2_value |= HI_OPTION_EARLY_CFG_DONE;
|
||||
rv = hif_diag_write_access(hif_hdl, flag2_targ_addr,
|
||||
flag2_value);
|
||||
if (rv != QDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: set option val (%d)", __func__, rv);
|
||||
goto done;
|
||||
}
|
||||
|
||||
hif_wake_target_cpu(scn);
|
||||
|
||||
done:
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_bus_configure() - configure the pcie bus
|
||||
* @hif_sc: pointer to the hif context.
|
||||
|
|
|
|||
Loading…
Reference in a new issue