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amd64_edac: Add support for newer F16h models
Extend ECC decoding support for F16h M30h. Tested on F16h M30h with ECC turned on using mce_amd_inj module and the patch works fine. Signed-off-by: Aravind Gopalakrishnan <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Tested-by: Arindam Nath <[email protected]> Acked-by: H. Peter Anvin <[email protected]> Signed-off-by: Borislav Petkov <[email protected]>
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4 changed files with 31 additions and 0 deletions
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@ -1807,6 +1807,17 @@ static struct amd64_family_type family_types[] = {
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.read_dct_pci_cfg = f10_read_dct_pci_cfg,
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}
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},
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[F16_M30H_CPUS] = {
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.ctl_name = "F16h_M30h",
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.f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1,
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.f3_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F3,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f16_dbam_to_chip_select,
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.read_dct_pci_cfg = f10_read_dct_pci_cfg,
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}
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},
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};
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/*
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@ -2586,6 +2597,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
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break;
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case 0x16:
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if (pvt->model == 0x30) {
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fam_type = &family_types[F16_M30H_CPUS];
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pvt->ops = &family_types[F16_M30H_CPUS].ops;
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break;
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}
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fam_type = &family_types[F16_CPUS];
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pvt->ops = &family_types[F16_CPUS].ops;
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break;
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@ -2838,6 +2854,14 @@ static const struct pci_device_id amd64_pci_table[] = {
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.class = 0,
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.class_mask = 0,
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},
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{
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.class = 0,
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.class_mask = 0,
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},
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{0, }
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};
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@ -168,6 +168,8 @@
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#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
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#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
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#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
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/*
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* Function 1 - Address Map
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@ -300,6 +302,7 @@ enum amd_families {
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F15_CPUS,
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F15_M30H_CPUS,
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F16_CPUS,
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F16_M30H_CPUS,
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NUM_FAMILIES,
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};
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