From 85c1763b51792b556bac6b5e7cb7cee85a0cd540 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Tue, 7 Jul 2020 18:37:47 +0530 Subject: [PATCH] ARM: dts: msm: Add GPU properties for Shima Add required GPU properties for Shima to enable graphics driver functionality. Change-Id: Ia14ac0269e3718d76177f594be25cf5dabbcdf55 --- qcom/shima-gpu.dtsi | 441 ++++++++++++++++++++++++++++++++++++++++++++ qcom/shima.dtsi | 20 ++ 2 files changed, 461 insertions(+) create mode 100644 qcom/shima-gpu.dtsi diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi new file mode 100644 index 000000000000..592e15ada5e6 --- /dev/null +++ b/qcom/shima-gpu.dtsi @@ -0,0 +1,441 @@ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a660_zap"; + memory-region = <&pil_gpu_micro_code_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { + compatible = "qcom,kgsl-3d0", + "qcom,adreno-gpu-a660-shima"; + status = "ok"; + + reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, + <0x3de0000 0x10000>, <0x3d8b000 0x2000>, + <0x06900000 0x80000>; + + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", + "isense_cntl", "qdss_gfx"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&aopcc QDSS_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "apb_pclk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; + + qcom,chipid = <0x06060001>; + + qcom,no-nap; + + qcom,highest-bank-bit = <15>; + qcom,min-access-length = <32>; + qcom,ubwc-mode = <4>; + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + ; /* index=11 */ + + qcom,bus-table-ddr8 = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + ; /* index=11 */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin"; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calculated as FMAX/4.8 MHz round up to zero + * decimal places plus two margin to account for + * clock jitters. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <285000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <8>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <75>; + qcom,initial-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <285000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <8>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <84>; + qcom,initial-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <390000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <285000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <8>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <95>; + qcom,initial-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <285000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <8>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <159>; + qcom,initial-pwrlevel = <5>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <752000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <9>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <285000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <8>; + }; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x03da0000 0x20000>; + + vddcx-supply = <&gpu_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x400>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x400>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x400>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d69000 { + compatible = "qcom,gpu-gmu"; + + reg = <0x3d6a000 0x30000>, + <0xb290000 0x10000>; + + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; + + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + + gmu_user: gmu_user { + compatible = "qcom,smmu-gmu-user-cb"; + iommus = <&kgsl_smmu 0x4 0x400>; + qcom,iommu-dma = "disabled"; + }; + + gmu_kernel: gmu_kernel { + compatible = "qcom,smmu-gmu-kernel-cb"; + iommus = <&kgsl_smmu 0x5 0x400>; + qcom,iommu-dma = "disabled"; + }; + + }; +}; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 985830d4a0d1..cebccd8a991e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2119,6 +2119,25 @@ qcom,dump-id = <0x104>; }; }; + + qfprom: qfprom@780000 { + compatible = "qcom,qfprom"; + reg = <0x780000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@1e1 { + reg = <0x1e1 0x2>; + bits = <5 8>; + }; + + gpu_gaming_bin: gpu_gaming_bin@1ed { + reg = <0x1ed 0x1>; + bits = <5 1>; + }; + }; }; #include "shima-pinctrl.dtsi" @@ -2134,6 +2153,7 @@ #include "msm-arm-smmu-shima.dtsi" #include "shima-vidc.dtsi" #include "shima-thermal.dtsi" +#include "shima-gpu.dtsi" &gcc_pcie_0_gdsc { status = "ok";