mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "ARM: dts: msm: Add support for target SM4250" into camera-kernel.lnx.1.0
This commit is contained in:
Camera Software Integration
Gerrit - the friendly Code Review server
commit
85dbb3c359
1 changed files with 686 additions and 0 deletions
686
bengal-camera.dtsi
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686
bengal-camera.dtsi
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@ -0,0 +1,686 @@
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#include <dt-bindings/msm/msm-camera.h>
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&soc {
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qcom,cam-req-mgr {
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compatible = "qcom,cam-req-mgr";
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status = "ok"
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};
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qcom,cam_smmu {
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compatible = "qcom,msm-cam-smmu";
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status = "ok"
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msm_cam_smmu_tfe {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0x400 0x000>,
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<&apps_smmu 0x401 0x000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
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label = "tfe";
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tfe_iova_mem_map: iova-mem-map {
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/* IO region is approximately 3.4 GB */
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iova-mem-region-io {
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iova-region-name = "io";
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iova-region-start = <0x7400000>;
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iova-region-len = <0xd8c00000>;
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iova-region-id = <0x3>;
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status = "ok"
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};
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};
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};
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msm_cam_smmu_ope {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0x820 0x000>,
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<&apps_smmu 0x821 0x020>,
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<&apps_smmu 0x840 0x000>,
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<&apps_smmu 0x841 0x000>;
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qcom,iommu-faults = "non-fatal";
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multiple-client-devices;
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qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
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label = "ope", "ope-cdm0";
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ope_iova_mem_map: iova-mem-map {
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/* IO region is approximately 3.4 GB */
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iova-mem-region-io {
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iova-region-name = "io";
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iova-region-start = <0x7400000>;
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iova-region-len = <0xd8c00000>;
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iova-region-id = <0x3>;
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status = "ok"
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};
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};
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};
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msm_cam_smmu_cpas_cdm {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0x800 0x000>,
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<&apps_smmu 0x801 0x020>;
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label = "cpas-cdm0";
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
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cpas_cdm_iova_mem_map: iova-mem-map {
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iova-mem-region-io {
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/* IO region is approximately 3.4 GB */
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iova-region-name = "io";
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iova-region-start = <0x7400000>;
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iova-region-len = <0xd8c00000>;
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iova-region-id = <0x3>;
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status = "ok"
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};
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};
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};
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msm_cam_smmu_secure {
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compatible = "qcom,msm-cam-smmu-cb";
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label = "cam-secure";
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qcom,secure-cb;
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};
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};
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qcom,cam-cpas@5c11000 {
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cell-index = <0>;
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compatible = "qcom,cam-cpas";
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label = "cpas";
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arch-compat = "cpas_top";
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status = "ok"
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reg-names = "cam_cpas_top", "cam_camnoc";
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reg = <0x5c11000 0x1000>,
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<0x5c13000 0x4000>;
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reg-cam-base = <0x11000 0x13000>;
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interrupt-names = "cpas_camnoc";
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interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
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camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
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regulator-names = "camss-vdd";
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camss-vdd-supply = <&gcc_camss_top_gdsc>;
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clock-names =
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"gcc_camss_ahb_clk",
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"gcc_camss_top_ahb_clk",
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"gcc_camss_top_ahb_clk_src",
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"gcc_camss_axi_clk",
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"gcc_camss_axi_clk_src";
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clocks =
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<&gcc GCC_CAMERA_AHB_CLK>,
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<&gcc GCC_CAMSS_TOP_AHB_CLK>,
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<&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
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<&gcc GCC_CAMSS_AXI_CLK>,
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<&gcc GCC_CAMSS_AXI_CLK_SRC>;
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src-clock-name = "gcc_camss_axi_clk_src";
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clock-rates =
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<0 0 0 0 0>,
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<0 80000000 80000000 19200000 19200000>,
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<0 80000000 80000000 150000000 150000000>,
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<0 80000000 80000000 200000000 200000000>,
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<0 80000000 80000000 300000000 300000000>,
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<0 80000000 80000000 300000000 300000000>,
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<0 80000000 80000000 300000000 300000000>;
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clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
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"svs_l1", "nominal", "turbo";
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control-camnoc-axi-clk;
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camnoc-bus-width = <32>;
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camnoc-axi-clk-bw-margin-perc = <20>;
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qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/
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qcom,msm-bus,num-cases = <7>; /*Need to verify*/
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qcom,msm-bus,num-paths = <1>; /*Need to verify*/
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qcom,msm-bus,vectors-KBps = /*Need to verify*/
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
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<MSM_BUS_MASTER_AMPSS_M0
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MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
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vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
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RPMH_REGULATOR_LEVEL_MIN_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_SVS
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RPMH_REGULATOR_LEVEL_SVS_L1
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM_L1
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RPMH_REGULATOR_LEVEL_NOM_L2
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RPMH_REGULATOR_LEVEL_TURBO
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RPMH_REGULATOR_LEVEL_TURBO_L1>;
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vdd-corner-ahb-mapping = "suspend", "minsvs",
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"lowsvs", "svs", "svs_l1",
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"nominal", "nominal", "nominal",
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"turbo", "turbo";
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client-id-based;
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client-names =
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"csiphy0", "csiphy1", "csiphy2", "csiphy3",
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"csiphy4", "csiphy5", "cci0", "cci1",
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"csid0", "csid1", "csid2", "tfe0",
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"tfe1", "tfe2", "ope0", "cam-cdm-intf0",
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"cpas-cdm0", "ope-cdm0", "tpg0", "tpg1";
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camera-bus-nodes {
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level2-nodes {
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level-index = <2>;
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level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum {
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cell-index = <0>;
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node-name = "level2-rt0-rd-wr-sum";
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traffic-merge-type =
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<CAM_CPAS_TRAFFIC_MERGE_SUM>;
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qcom,axi-port-name = "cam_hf_0";
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ib-bw-voting-needed;
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qcom,axi-port-mnoc {
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qcom,msm-bus,name =
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"cam_hf_0_mnoc";
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qcom,msm-bus-vector-dyn-vote;
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_CAMNOC_HF
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MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_CAMNOC_HF
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MSM_BUS_SLAVE_EBI_CH0 0 0>;
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};
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};
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level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum {
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cell-index = <1>;
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node-name = "level2-nrt0-rd-wr-sum";
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traffic-merge-type =
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<CAM_CPAS_TRAFFIC_MERGE_SUM>;
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qcom,axi-port-name = "cam_sf_0";
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qcom,axi-port-mnoc {
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qcom,msm-bus,name =
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"cam_sf_0_mnoc";
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qcom,msm-bus-vector-dyn-vote;
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_CAMNOC_SF
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MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_CAMNOC_SF
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MSM_BUS_SLAVE_EBI_CH0 0 0>;
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};
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};
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};
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level1-nodes {
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level-index = <1>;
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camnoc-max-needed;
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level1_rt0_wr: level1-rt0-wr {
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cell-index = <2>;
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node-name = "level1-rt0-wr";
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parent-node = <&level2_rt0_rd_wr_sum>;
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traffic-merge-type =
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<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
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};
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level1_nrt0_rd_wr: level1-nrt0-rd-wr {
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cell-index = <3>;
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node-name = "level1-nrt0-rd-wr";
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parent-node = <&level2_nrt0_rd_wr_sum>;
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traffic-merge-type =
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<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
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};
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};
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level0-nodes {
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level-index = <0>;
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ope0_all_wr: ope0-all-wr {
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cell-index = <4>;
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node-name = "ope0-all-wr";
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client-name = "ope0";
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traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
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traffic-transaction-type =
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<CAM_CPAS_TRANSACTION_WRITE>;
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parent-node = <&level1_nrt0_rd_wr>;
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};
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ope0_all_rd: ope0-all-rd {
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cell-index = <5>;
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node-name = "ope0-all-rd";
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client-name = "ope0";
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traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
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traffic-transaction-type =
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<CAM_CPAS_TRANSACTION_READ>;
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parent-node = <&level1_nrt0_rd_wr>;
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};
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tfe0_all_wr: tfe0-all-wr {
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cell-index = <6>;
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node-name = "tfe0-all-wr";
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client-name = "tfe0";
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traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
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traffic-transaction-type =
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<CAM_CPAS_TRANSACTION_WRITE>;
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constituent-paths =
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<CAM_CPAS_PATH_DATA_IFE_RDI0
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CAM_CPAS_PATH_DATA_IFE_RDI1
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CAM_CPAS_PATH_DATA_IFE_RDI2
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CAM_CPAS_PATH_DATA_IFE_RDI3
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CAM_CPAS_PATH_DATA_IFE_VID
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CAM_CPAS_PATH_DATA_IFE_DISP
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CAM_CPAS_PATH_DATA_IFE_STATS>;
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parent-node = <&level1_rt0_wr>;
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};
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tfe1_all_wr: tfe1-all-wr {
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cell-index = <7>;
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node-name = "tfe1-all-wr";
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client-name = "tfe1";
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traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
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traffic-transaction-type =
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<CAM_CPAS_TRANSACTION_WRITE>;
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constituent-paths =
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<CAM_CPAS_PATH_DATA_IFE_RDI0
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CAM_CPAS_PATH_DATA_IFE_RDI1
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CAM_CPAS_PATH_DATA_IFE_RDI2
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CAM_CPAS_PATH_DATA_IFE_RDI3
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CAM_CPAS_PATH_DATA_IFE_VID
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CAM_CPAS_PATH_DATA_IFE_DISP
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CAM_CPAS_PATH_DATA_IFE_STATS>;
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parent-node = <&level1_rt0_wr>;
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};
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tfe2_all_wr: tfe2-all-wr {
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cell-index = <8>;
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node-name = "tfe2-all-wr";
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client-name = "tfe2";
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traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
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traffic-transaction-type =
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<CAM_CPAS_TRANSACTION_WRITE>;
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constituent-paths =
|
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<CAM_CPAS_PATH_DATA_IFE_RDI0
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CAM_CPAS_PATH_DATA_IFE_RDI1
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CAM_CPAS_PATH_DATA_IFE_RDI2
|
||||
CAM_CPAS_PATH_DATA_IFE_RDI3
|
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CAM_CPAS_PATH_DATA_IFE_VID
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CAM_CPAS_PATH_DATA_IFE_DISP
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CAM_CPAS_PATH_DATA_IFE_STATS>;
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||||
parent-node = <&level1_rt0_wr>;
|
||||
};
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||||
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||||
cpas_cdm0_all_rd: cpas-cdm0-all-rd {
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||||
cell-index = <9>;
|
||||
node-name = "cpas-cdm0-all-rd";
|
||||
client-name = "cpas-cdm0";
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traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
||||
traffic-transaction-type =
|
||||
<CAM_CPAS_TRANSACTION_READ>;
|
||||
parent-node = <&level1_nrt0_rd_wr>;
|
||||
};
|
||||
|
||||
ope_cdm0_all_rd: ope-cdm0-all-rd {
|
||||
cell-index = <10>;
|
||||
node-name = "ope-cdm0-all-rd";
|
||||
client-name = "ope-cdm0";
|
||||
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
||||
traffic-transaction-type =
|
||||
<CAM_CPAS_TRANSACTION_READ>;
|
||||
parent-node = <&level1_nrt0_rd_wr>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,cam-cdm-intf {
|
||||
compatible = "qcom,cam-cdm-intf";
|
||||
cell-index = <0>;
|
||||
label = "cam-cdm-intf";
|
||||
num-hw-cdm = <2>;
|
||||
cdm-client-names = "vfe";
|
||||
status = "ok"
|
||||
};
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||||
|
||||
cam_cpas_cdm: qcom,cpas-cdm0@5c23000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,cam-cpas-cdm2_0";
|
||||
label = "cpas-cdm";
|
||||
reg = <0x5c23000 0x400>;
|
||||
reg-names = "cpas-cdm0";
|
||||
reg-cam-base = <0x23000>;
|
||||
interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "cpas-cdm0";
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names = "cam_cc_cpas_top_ahb_clk";
|
||||
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>;
|
||||
clock-rates = <0>;
|
||||
clock-cntl-level = "svs";
|
||||
cdm-client-names = "tfe0", "tfe1", "tfe2";
|
||||
config-fifo;
|
||||
fifo-depths = <64 64 64 64>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_ope_cdm: qcom,ope-cdm0@5c42000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,cam-ope-cdm2_0";
|
||||
label = "ope-cdm";
|
||||
reg = <0x5c42000 0x400>;
|
||||
reg-names = "ope-cdm0";
|
||||
reg-cam-base = <0x42000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ope-cdm0";
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"ope_ahb_clk",
|
||||
"ope_clk_src",
|
||||
"ope_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_OPE_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_OPE_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_OPE_CLK>;
|
||||
clock-rates = <0 0 0>,
|
||||
<0 0 0>,
|
||||
<0 0 0>,
|
||||
<0 0 0>;
|
||||
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||||
cdm-client-names = "ope";
|
||||
config-fifo;
|
||||
fifo-depths = <64 64 64 64>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
qcom,cam-isp {
|
||||
compatible = "qcom,cam-isp";
|
||||
arch-compat = "tfe";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe_csid0: qcom,tfe_csid0@5c6e000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,csid530";
|
||||
reg-names = "csid", "top", "camnoc";
|
||||
reg = <0x5c6e000 0x5000>,
|
||||
<0x5c11000 0x1000>,
|
||||
<0x5c13000 0x4000>;
|
||||
reg-cam-base = <0x6e000 0x11000 0x13000>;
|
||||
interrupt-names = "csid0";
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"tfe_csid_clk_src",
|
||||
"tfe_csid_clk",
|
||||
"cphy_rx_clk_src",
|
||||
"tfe_cphy_rx_clk",
|
||||
"tfe_clk_src",
|
||||
"tfe_clk",
|
||||
"tfe_axi_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
|
||||
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
|
||||
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_0_CLK>,
|
||||
<&gcc GCC_CAMSS_AXI_CLK>;
|
||||
clock-rates =
|
||||
<240000000 240000000 0 240000000 256000000 256000000 150000000>,
|
||||
<384000000 384000000 0 341333333 460800000 460800000 200000000>,
|
||||
<426400000 426400000 0 384000000 576000000 576000000 300000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "tfe_csid_clk_src";
|
||||
clock-control-debugfs = "true";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe0: qcom,tfe0@5c6e000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,tfe530";
|
||||
reg-names = "tfe0";
|
||||
reg = <0x5c6e000 0x5000>;
|
||||
reg-cam-base = <0x6e000>;
|
||||
interrupt-names = "tfe0";
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"tfe_clk_src",
|
||||
"tfe_clk",
|
||||
"tfe_axi_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_0_CLK>,
|
||||
<&gcc GCC_CAMSS_AXI_CLK>;
|
||||
clock-rates =
|
||||
<256000000 256000000 150000000>,
|
||||
<460800000 460800000 200000000>,
|
||||
<576000000 576000000 300000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "tfe_clk_src";
|
||||
clock-control-debugfs = "true";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe_csid1: qcom,tfe_csid1@5c75000 {
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,csid530";
|
||||
reg-names = "csid", "top", "camnoc";
|
||||
reg = <0x5c75000 0x5000>,
|
||||
<0x5c11000 0x1000>,
|
||||
<0x5c13000 0x4000>;
|
||||
reg-cam-base = <0x75000 0x11000 0x13000>;
|
||||
interrupt-names = "csid1";
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"tfe_csid_clk_src",
|
||||
"tfe_csid_clk",
|
||||
"cphy_rx_clk_src",
|
||||
"tfe_cphy_rx_clk",
|
||||
"tfe_clk_src",
|
||||
"tfe_clk",
|
||||
"tfe_axi_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
|
||||
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
|
||||
<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_1_CLK>,
|
||||
<&gcc GCC_CAMSS_AXI_CLK>;
|
||||
clock-rates =
|
||||
<240000000 240000000 0 240000000 256000000 256000000 150000000>,
|
||||
<384000000 384000000 0 341333333 460800000 460800000 200000000>,
|
||||
<426400000 426400000 0 384000000 576000000 576000000 300000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "tfe_csid_clk_src";
|
||||
clock-control-debugfs = "true";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe1: qcom,tfe1@5c75000 {
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,tfe530";
|
||||
reg-names = "tfe1";
|
||||
reg = <0x5c75000 0x5000>;
|
||||
reg-cam-base = <0x75000>;
|
||||
interrupt-names = "tfe1";
|
||||
interrupts = <0 213 0>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"tfe_clk_src",
|
||||
"tfe_clk",
|
||||
"tfe_axi_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_1_CLK>,
|
||||
<&gcc GCC_CAMSS_AXI_CLK>;
|
||||
clock-rates =
|
||||
<256000000 256000000 150000000>,
|
||||
<460800000 460800000 200000000>,
|
||||
<576000000 576000000 300000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "tfe_clk_src";
|
||||
clock-control-debugfs = "true";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe_csid2: qcom,tfe_csid2@5c7c000 {
|
||||
cell-index = <2>;
|
||||
compatible = "qcom,csid530";
|
||||
reg-names = "csid", "top", "camnoc";
|
||||
reg = <0x5c7c000 0x5000>,
|
||||
<0x5c11000 0x1000>,
|
||||
<0x5c13000 0x4000>;
|
||||
reg-cam-base = <0x7c000 0x11000 0x13000>;
|
||||
interrupt-names = "csid2";
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"tfe_csid_clk_src",
|
||||
"tfe_csid_clk",
|
||||
"cphy_rx_clk_src",
|
||||
"tfe_cphy_rx_clk",
|
||||
"tfe_clk_src",
|
||||
"tfe_clk",
|
||||
"tfe_axi_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_2_CSID_CLK>,
|
||||
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>,
|
||||
<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_2_CLK>,
|
||||
<&gcc GCC_CAMSS_AXI_CLK>;
|
||||
clock-rates =
|
||||
<240000000 240000000 0 240000000 256000000 256000000 150000000>,
|
||||
<384000000 384000000 0 341333333 460800000 460800000 200000000>,
|
||||
<426400000 426400000 0 384000000 576000000 576000000 300000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "tfe_csid_clk_src";
|
||||
clock-control-debugfs = "true";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe2: qcom,tfe2@5c7c000 {
|
||||
cell-index = <2>;
|
||||
compatible = "qcom,tfe530";
|
||||
reg-names = "tfe2";
|
||||
reg = <0x5c7c000 0x5000>;
|
||||
reg-cam-base = <0x7c000>;
|
||||
interrupt-names = "tfe2";
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"tfe_clk_src",
|
||||
"tfe_clk",
|
||||
"tfe_axi_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_2_CLK>,
|
||||
<&gcc GCC_CAMSS_AXI_CLK>;
|
||||
clock-rates =
|
||||
<256000000 256000000 150000000>,
|
||||
<460800000 460800000 200000000>,
|
||||
<576000000 576000000 300000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "tfe_clk_src";
|
||||
clock-control-debugfs = "true";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe_tpg0: qcom,tpg0@5c66000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,tpgv1";
|
||||
reg-names = "tpg0", "top";
|
||||
reg = <0x5c66000 0x400>,
|
||||
<0x5c11000 0x1000>;
|
||||
reg-cam-base = <0x66000 0x11000>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"cphy_rx_clk_src",
|
||||
"tfe_0_cphy_rx_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>;
|
||||
clock-rates =
|
||||
<240000000 240000000>,
|
||||
<341333333 341333333>,
|
||||
<384000000 384000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "cphy_rx_clk_src";
|
||||
clock-control-debugfs = "false";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
cam_tfe_tpg1: qcom,tpg0@5c68000 {
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,tpgv1";
|
||||
reg-names = "tpg0", "top";
|
||||
reg = <0x5c68000 0x400>,
|
||||
<0x5c11000 0x1000>;
|
||||
reg-cam-base = <0x68000 0x11000>;
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"cphy_rx_clk_src",
|
||||
"tfe_1_cphy_rx_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
|
||||
clock-rates =
|
||||
<240000000 240000000>,
|
||||
<341333333 341333333>,
|
||||
<384000000 384000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "turbo";
|
||||
src-clock-name = "cphy_rx_clk_src";
|
||||
clock-control-debugfs = "false";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
qcom,cam-ope {
|
||||
compatible = "qcom,cam-ope";
|
||||
compat-hw-name = "qcom,ope";
|
||||
num-ope = <1>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
ope: qcom,ope@0x5c42000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,ope";
|
||||
reg =
|
||||
<0x5c42000 0x400>,
|
||||
<0x5c42400 0x200>,
|
||||
<0x5c42600 0x200>,
|
||||
<0x5c42800 0x4400>,
|
||||
<0x5c46c00 0x190>,
|
||||
<0x5c46d90 0x1270>;
|
||||
reg-names =
|
||||
"ope_cdm",
|
||||
"ope_top",
|
||||
"ope_qos",
|
||||
"ope_pp",
|
||||
"ope_bus_rd",
|
||||
"ope_bus_wr";
|
||||
reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>;
|
||||
interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ope";
|
||||
regulator-names = "camss";
|
||||
camss-supply = <&gcc_camss_top_gdsc>;
|
||||
clock-names =
|
||||
"ope_ahb_clk",
|
||||
"ope_clk_src",
|
||||
"ope_clk";
|
||||
clocks =
|
||||
<&gcc GCC_CAMSS_OPE_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_OPE_CLK_SRC>,
|
||||
<&gcc GCC_CAMSS_OPE_CLK>;
|
||||
clock-rates =
|
||||
<171428571 200000000 200000000>,
|
||||
<171428571 266600000 266600000>,
|
||||
<240000000 465000000 465000000>,
|
||||
<240000000 580000000 580000000>;
|
||||
clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
|
||||
src-clock-name = "ope_clk_src";
|
||||
status = "ok"
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue