From 86162602c53b4b92ef7014aa9ccbae115b51f97e Mon Sep 17 00:00:00 2001 From: Yujun Zhang Date: Thu, 9 May 2019 23:22:43 +0800 Subject: [PATCH] disp: msm: dsi: Fix incorrect DSI PHY timing of version 4 For DSI PHY timing of version 4, adds the missing configuation of phy_clk_params and updates some extra clock parameters. The less precision during calculation is fixed, which is caused by not exactly following PHY timing document. Change-Id: Ibb75d4d3e5b4a5979ff4a85dba1accf3677a6584 Signed-off-by: Yujun Zhang --- msm/dsi/dsi_phy_timing_calc.c | 11 ++++------- msm/dsi/dsi_phy_timing_v4_0.c | 27 +++++++++++++++------------ 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/msm/dsi/dsi_phy_timing_calc.c b/msm/dsi/dsi_phy_timing_calc.c index 70e7ee3d6a8b..a06d00dd6c13 100644 --- a/msm/dsi/dsi_phy_timing_calc.c +++ b/msm/dsi/dsi_phy_timing_calc.c @@ -474,9 +474,8 @@ static int calc_clk_post(struct dsi_phy_hw *phy, t->rec_max = 255; /* register value */ - rec_cal1 = (t->rec_max - t->rec_min); - rec_cal2 = clk_params->clk_post_buf/100; - t->rec = rec_cal1 * rec_cal2 + t->rec_min; + t->rec = DIV_ROUND_UP((((t->rec_max - t->rec_min) * + clk_params->clk_post_buf) + (t->rec_min * 100)), 100); rc = dsi_phy_cmn_validate_and_set(t, "clk_post"); if (rc) @@ -501,7 +500,6 @@ static int calc_clk_pre(struct dsi_phy_hw *phy, s64 rec_temp1; s64 clk_prepare, clk_zero, clk_16; u32 input1; - s64 rec_cal1, rec_cal2; /* mipi min */ t->mipi_min = cal_clk_pulse_time(8, 0, clk_params->bitclk_mbps); @@ -526,9 +524,8 @@ static int calc_clk_pre(struct dsi_phy_hw *phy, t->rec_max = 255; /* register value */ - rec_cal1 = (t->rec_max - t->rec_min); - rec_cal2 = clk_params->clk_pre_buf/100; - t->rec = rec_cal1 * rec_cal2 + t->rec_min; + t->rec =DIV_ROUND_UP((((t->rec_max - t->rec_min) * + 125) + (t->rec_min * 100 * 100)), 100 * 100); rc = dsi_phy_cmn_validate_and_set(t, "clk_pre"); if (rc) diff --git a/msm/dsi/dsi_phy_timing_v4_0.c b/msm/dsi/dsi_phy_timing_v4_0.c index d7c9bde87e46..5a1c89b55e53 100644 --- a/msm/dsi/dsi_phy_timing_v4_0.c +++ b/msm/dsi/dsi_phy_timing_v4_0.c @@ -9,21 +9,24 @@ void dsi_phy_hw_v4_0_get_default_phy_params( struct phy_clk_params *params) { - params->clk_prep_buf = 0; - params->clk_zero_buf = 0; - params->clk_trail_buf = 0; - params->hs_prep_buf = 0; - params->hs_zero_buf = 0; - params->hs_trail_buf = 0; + params->clk_prep_buf = 50; + params->clk_zero_buf = 2; + params->clk_trail_buf = 30; + params->hs_prep_buf = 50; + params->hs_zero_buf = 10; + params->hs_trail_buf = 30; params->hs_rqst_buf = 0; - params->hs_exit_buf = 0; + params->hs_exit_buf = 10; + /* 1.25 is used in code for precision */ + params->clk_pre_buf = 1; + params->clk_post_buf = 5; } int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult) { s64 rec_temp2, rec_temp3; - rec_temp2 = (rec_temp1 - mult); + rec_temp2 = rec_temp1; rec_temp3 = roundup(div_s64(rec_temp2, 8), mult); return (div_s64(rec_temp3, mult) - 1); } @@ -33,7 +36,7 @@ int32_t dsi_phy_hw_v4_0_calc_clk_trail_rec_min(s64 temp_mul, { s64 rec_temp1, rec_temp2, rec_temp3; - rec_temp1 = temp_mul + frac; + rec_temp1 = temp_mul; rec_temp2 = div_s64(rec_temp1, 8); rec_temp3 = roundup(rec_temp2, mult); return (div_s64(rec_temp3, mult) - 1); @@ -84,11 +87,11 @@ void dsi_phy_hw_v4_0_update_timing_params( timing->lane_v4[6] = desc->hs_prepare.reg_value; timing->lane_v4[7] = desc->hs_trail.reg_value; timing->lane_v4[8] = desc->hs_rqst.reg_value; - timing->lane_v4[9] = 0x03; + timing->lane_v4[9] = 0x02; timing->lane_v4[10] = 0x04; timing->lane_v4[11] = 0x00; - timing->lane_v4[12] = 0x00; - timing->lane_v4[13] = 0x00; + timing->lane_v4[12] = desc->clk_pre.reg_value; + timing->lane_v4[13] = desc->clk_post.reg_value; pr_debug("[%d %d %d %d]\n", timing->lane_v4[0], timing->lane_v4[1], timing->lane_v4[2], timing->lane_v4[3]);