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[SPARC64]: SUN4U PCI-E controller support.
Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <[email protected]>
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7 changed files with 535 additions and 22 deletions
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@ -32,6 +32,7 @@ struct iommu {
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unsigned long iommu_control;
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unsigned long iommu_tsbbase;
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unsigned long iommu_flush;
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unsigned long iommu_flushinv;
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unsigned long iommu_ctxflush;
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unsigned long write_complete_reg;
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unsigned long dummy_page;
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