From 7c24be2766de6a038b4386a50aadc10ec4fcf480 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 19 Jan 2021 15:52:51 +0800 Subject: [PATCH] ARM: dts: msm: Disable SDCC TPDMs on shima Disable all SDCC TPDMs on shima first since there is SDCC internal clock issue. Change-Id: Iac18333769fa593a407b10eeed830e728d475c1a --- qcom/shima-coresight.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index 90cccf9a0f3b..471a736d4b05 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -1210,6 +1210,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-4"; clocks = <&aopcc QDSS_CLK>; @@ -1372,6 +1373,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-1"; clocks = <&aopcc QDSS_CLK>; @@ -1394,6 +1396,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-2"; clocks = <&aopcc QDSS_CLK>;