mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 22:40:54 -04:00
Merge "ARM: dts: msm: Enable usb host for scuba"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
86b6196bb9
4 changed files with 477 additions and 100 deletions
127
qcom/pm8008.dtsi
Normal file
127
qcom/pm8008.dtsi
Normal file
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@ -0,0 +1,127 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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pm8008_8: qcom,pm8008@8 {
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compatible = "qcom,i2c-pmic";
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reg = <0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-names = "pm8008";
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qcom,periph-map = <0x09 0x24 0xc0 0xc1>;
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pm8008_chip: qcom,pm8008-chip@900 {
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compatible = "qcom,pm8008-chip";
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reg = <0x900>;
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interrupts = <0x09 4 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ocp";
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PM8008_EN: qcom,pm8008-chip-en {
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regulator-name = "pm8008-chip-en";
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};
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};
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qcom,revid@100 {
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compatible = "qcom,qpnp-revid";
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reg = <0x100>;
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};
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pm8008_gpios: pinctrl@c000 {
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compatible = "qcom,spmi-gpio";
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reg = <0xc000 0x200>;
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interrupts = <0xc0 0 IRQ_TYPE_EDGE_RISING>,
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<0xc1 0 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "pm8008_gpio1", "pm8008_gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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pm8008_gpio1_active: pm8008_gpio1_active {
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pins = "gpio1";
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function = "func1";
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power-source = <1>;
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output-enable;
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input-disable;
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bias-disable;
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};
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};
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};
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pm8008_9: qcom,pm8008@9 {
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compatible = "qcom,i2c-pmic";
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reg = <0x9>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pm8008_gpio1_active>;
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pm8008_regulators: qcom,pm8008-regulator {
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compatible = "qcom,pm8008-regulator";
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pm8008_en-supply = <&PM8008_EN>;
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qcom,enable-ocp-broadcast;
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L1P: qcom,pm8008-l1@4000 {
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reg = <0x4000>;
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regulator-name = "pm8008_l1";
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regulator-min-microvolt = <528000>;
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regulator-max-microvolt = <1504000>;
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qcom,min-dropout-voltage = <225000>;
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qcom,hpm-min-load = <10000>;
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};
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L2P: qcom,pm8008-l2@4100 {
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reg = <0x4100>;
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regulator-name = "pm8008_l2";
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regulator-min-microvolt = <528000>;
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regulator-max-microvolt = <1504000>;
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qcom,min-dropout-voltage = <225000>;
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qcom,hpm-min-load = <10000>;
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};
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L3P: qcom,pm8008-l3@4200 {
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reg = <0x4200>;
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regulator-name = "pm8008_l3";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <3400000>;
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qcom,min-dropout-voltage = <200000>;
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qcom,hpm-min-load = <10000>;
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};
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L4P: qcom,pm8008-l4@4300 {
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reg = <0x4300>;
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regulator-name = "pm8008_l4";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <3400000>;
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qcom,min-dropout-voltage = <200000>;
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qcom,hpm-min-load = <10000>;
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};
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L5P: qcom,pm8008-l5@4400 {
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reg = <0x4400>;
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regulator-name = "pm8008_l5";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <3400000>;
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qcom,min-dropout-voltage = <300000>;
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qcom,hpm-min-load = <10000>;
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};
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L6P: qcom,pm8008-l6@4400 {
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reg = <0x4500>;
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regulator-name = "pm8008_l6";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <3400000>;
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qcom,min-dropout-voltage = <300000>;
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qcom,hpm-min-load = <10000>;
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};
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L7P: qcom,pm8008-l7@4400 {
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reg = <0x4600>;
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regulator-name = "pm8008_l7";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <3400000>;
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qcom,min-dropout-voltage = <300000>;
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qcom,hpm-min-load = <10000>;
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};
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};
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};
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@ -77,3 +77,11 @@
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"chg_temp";
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qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
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};
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&qusb_phy0 {
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extcon = <&pm2250_charger>;
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};
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&usb0 {
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extcon = <&qusb_phy0>, <&eud>;
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};
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308
qcom/qrb2210-rb1-usb.dtsi
Normal file
308
qcom/qrb2210-rb1-usb.dtsi
Normal file
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@ -0,0 +1,308 @@
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#include <dt-bindings/clock/qcom,gcc-scuba.h>
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#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@4e00000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x4e00000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x0120 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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dpdm-supply = <&qusb_phy0>;
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qcom,core-clk-rate = <133333333>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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qcom,gsi-disable-io-coherency;
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
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<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
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qcom,interconnect-values-nom = /* NOMINAL Votes */
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<1000000 1550000>,
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<0 2400>,
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<0 40000>;
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qcom,interconnect-values-svs = /* SVS Votes */
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<240000 700000>,
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<0 2400>,
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<0 40000>;
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dwc3@4e00000 {
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compatible = "snps,dwc3";
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reg = <0x4e00000 0xcd00>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
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tx-fifo-resize;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <0>;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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qcom,usbbam@0x04f04000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0x04f04000 0x17000>;
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interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
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qcom,usb-bam-fifo-baseaddr = <0xc121000>;
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qcom,usb-bam-num-pipes = <4>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x08064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related High Speed PHY */
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qusb_phy0: qusb@1613000 {
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compatible = "qcom,qusb2phy";
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reg = <0x01613000 0x180>,
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<0x003cb250 0x4>,
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<0x01b40258 0x4>,
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<0x01612000 0x4>;
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reg-names = "qusb_phy_base",
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"tcsr_clamp_dig_n_1p8",
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"tune2_efuse_addr",
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"eud_enable_reg";
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vdd-supply = <&pm2250_l12>;
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vdda18-supply = <&pm2250_l13>;
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vdda33-supply = <&pm2250_l21>;
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qcom,vdd-voltage-level = <0 925000 970000>;
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qcom,tune2-efuse-bit-pos = <25>;
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qcom,tune2-efuse-num-bits = <4>;
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qcom,qusb-phy-init-seq = <0xf8 0x80
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0xb3 0x84
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0x83 0x88
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0xc0 0x8c
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0x30 0x08
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0x79 0x0c
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0x21 0x10
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0x14 0x9c
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0x80 0x04
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0x9f 0x1c
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0x00 0x18>;
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phy_type = "utmi";
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qcom,phy-clk-scheme = "cmos";
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qcom,major-rev = <1>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_AHB2PHY_USB_CLK>;
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clock-names = "ref_clk_src", "cfg_ahb_clk";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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/* Primary USB port related QMP USB PHY */
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usb_qmp_phy: ssphy@1615000 {
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compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
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reg = <0x01615000 0x1000>,
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<0x03cb244 0x4>;
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reg-names = "qmp_phy_base",
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"vls_clamp_reg";
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vdd-supply = <&pm2250_l12>;
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core-supply = <&pm2250_l13>;
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qcom,vdd-voltage-level = <0 925000 970000>;
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qcom,core-voltage-level = <0 1800000 1800000>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14 0x00
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USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0x00
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USB3PHY_QSERDES_COM_CLK_SELECT 0x30 0x00
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USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x06 0x00
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USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00 0x00
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USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08 0x00
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USB3PHY_QSERDES_COM_BG_TRIM 0x0f 0x00
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USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0x00
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USB3PHY_QSERDES_COM_HSCLK_SEL 0x00 0x00
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USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82 0x00
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USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55 0x00
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USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x55 0x00
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USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x03 0x00
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USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0b 0x00
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USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0x00
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USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x28 0x00
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USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x80 0x00
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USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0x00
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USB3PHY_QSERDES_COM_CORECLK_DIV 0x0a 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00 0x00
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USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00 0x00
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USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00 0x00
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USB3PHY_QSERDES_COM_BG_TIMER 0x0a 0x00
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||||
USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01 0x00
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||||
USB3PHY_QSERDES_COM_SSC_PER1 0x31 0x00
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USB3PHY_QSERDES_COM_SSC_PER2 0x01 0x00
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USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00 0x00
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USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00 0x00
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USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0xde 0x00
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USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07 0x00
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USB3PHY_QSERDES_COM_PLL_IVCO 0x0f 0x00
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USB3PHY_QSERDES_COM_CMN_CONFIG 0x06 0x00
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||||
USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x80 0x00
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USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x01 0x00
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||||
USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0x00
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||||
USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0x00
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||||
USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x00 0x00
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USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x00 0x00
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||||
USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x00 0x00
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||||
USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x00 0x00
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||||
USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x00 0x00
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USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x00 0x00
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USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0a 0x00
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USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0a 0x00
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USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x06 0x00
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USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x06 0x00
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USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0x00
|
||||
USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0x00
|
||||
USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x02 0x00
|
||||
USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x02 0x00
|
||||
USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0x00
|
||||
USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0x00
|
||||
USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0x00
|
||||
USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0x00
|
||||
USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0x00
|
||||
USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0x00
|
||||
USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0x00
|
||||
USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0x00
|
||||
USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x0a 0x00
|
||||
USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x0a 0x00
|
||||
USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03 0x00
|
||||
USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03 0x00
|
||||
USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0x00
|
||||
USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0x00
|
||||
USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x00 0x00
|
||||
USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x00 0x00
|
||||
USB3PHY_QSERDES_RXA_RX_MODE_00 0x00 0x00
|
||||
USB3PHY_QSERDES_RXB_RX_MODE_00 0x00 0x00
|
||||
USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0x00
|
||||
USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0x00
|
||||
USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0x00
|
||||
USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0x00
|
||||
USB3PHY_QSERDES_TXA_LANE_MODE_1 0xc6 0x00
|
||||
USB3PHY_QSERDES_TXB_LANE_MODE_1 0xc6 0x00
|
||||
USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x00 0x00
|
||||
USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x00 0x00
|
||||
USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x00 0x00
|
||||
USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x00 0x00
|
||||
USB3PHY_PCS_TXMGN_V0 0x9f 0x00
|
||||
USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x17 0x00
|
||||
USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0f 0x00
|
||||
USB3PHY_PCS_FLL_CNTRL2 0x83 0x00
|
||||
USB3PHY_PCS_FLL_CNTRL1 0x02 0x00
|
||||
USB3PHY_PCS_FLL_CNT_VAL_L 0x09 0x00
|
||||
USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2 0x00
|
||||
USB3PHY_PCS_FLL_MAN_CODE 0x85 0x00
|
||||
USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1 0x00
|
||||
USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f 0x00
|
||||
USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47 0x00
|
||||
USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75 0x00
|
||||
USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13 0x00
|
||||
USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0x00
|
||||
USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0x00
|
||||
USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44 0x00
|
||||
USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0x00
|
||||
USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0x00
|
||||
USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40 0x00
|
||||
USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00 0x00
|
||||
USB3PHY_PCS_RX_SIGDET_LVL 0x88 0x00
|
||||
0xffffffff 0xffffffff 0x00>;
|
||||
|
||||
qcom,qmp-phy-reg-offset =
|
||||
<0xd74 /* USB3_PHY_PCS_STATUS */
|
||||
0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
|
||||
0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
|
||||
0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
|
||||
0xc00 /* USB3_PHY_SW_RESET */
|
||||
0xc08 /* USB3_PHY_START */
|
||||
0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
|
||||
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_AHB2PHY_USB_CLK>;
|
||||
|
||||
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||||
"ref_clk", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
|
||||
reset-names = "phy_reset", "phy_phy_reset";
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
usb_audio_qmi_dev {
|
||||
compatible = "qcom,usb-audio-qmi-dev";
|
||||
iommus = <&apps_smmu 0x1cf 0x0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
qcom,usb-audio-stream-id = <0xf>;
|
||||
qcom,usb-audio-intr-num = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -660,6 +660,23 @@
|
|||
|
||||
};
|
||||
|
||||
eud: qcom,msm-eud@1610000 {
|
||||
compatible = "qcom,msm-eud";
|
||||
interrupt-names = "eud_irq";
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x1610000 0x2000>,
|
||||
<0x1612000 0x1000>,
|
||||
<0x3E5018 0x4>;
|
||||
reg-names = "eud_base", "eud_mode_mgr2",
|
||||
"eud_tcsr_check_reg";
|
||||
qcom,secure-eud-en;
|
||||
qcom,eud-tcsr-check-enable;
|
||||
qcom,eud-clock-vote-req;
|
||||
clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
|
||||
clock-names = "eud_ahb2phy_clk";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
wdog: qcom,wdt@f017000 {
|
||||
compatible = "qcom,msm-watchdog";
|
||||
reg = <0xf017000 0x1000>;
|
||||
|
|
@ -672,7 +689,7 @@
|
|||
qcom,wakeup-enable;
|
||||
};
|
||||
|
||||
dcc: dcc_v2@1be2000 {
|
||||
dcc: dcc_v2@1be2000 {
|
||||
compatible = "qcom,dcc-v2";
|
||||
reg = <0x1be2000 0x1000>,
|
||||
<0x1bee000 0x2000>;
|
||||
|
|
@ -688,6 +705,11 @@ dcc: dcc_v2@1be2000 {
|
|||
rpm-channel-type = <15>; /* SMD_APPS_RPM */
|
||||
};
|
||||
|
||||
qcom,sps {
|
||||
compatible = "qcom,msm-sps-4k";
|
||||
qcom,pipe-attr-ee;
|
||||
};
|
||||
|
||||
mem_dump {
|
||||
compatible = "qcom,mem-dump";
|
||||
memory-region = <&dump_mem>;
|
||||
|
|
@ -1339,114 +1361,26 @@ dcc: dcc_v2@1be2000 {
|
|||
#include "msm-arm-smmu-qrb2210-rb1.dtsi"
|
||||
#include "qrb2210-rb1-qupv3.dtsi"
|
||||
#include "qrb2210-rb1-gdsc.dtsi"
|
||||
#include "qrb2210-rb1-usb.dtsi"
|
||||
|
||||
&qupv3_se1_i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "ok"
|
||||
|
||||
pm8008_8: qcom,pm8008@8 {
|
||||
compatible = "qcom,i2c-pmic";
|
||||
reg = <0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#include "pm8008.dtsi"
|
||||
};
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pm8008_active>;
|
||||
&pm8008_8 {
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
pm8008_chip: qcom,pm8008-chip@900 {
|
||||
compatible = "qcom,pm8008-chip";
|
||||
reg = <0x900>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
|
||||
};
|
||||
|
||||
PM8008_EN: qcom,pm8008-chip-en {
|
||||
regulator-name = "pm8008-chip-en";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,revid@100 {
|
||||
compatible = "qcom,qpnp-revid";
|
||||
reg = <0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8008_9: qcom,pm8008@9 {
|
||||
compatible = "qcom,i2c-pmic";
|
||||
reg = <0x9>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8008_regulators: qcom,pm8008-regulator {
|
||||
compatible = "qcom,pm8008-regulator";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pm8008_en-supply = <&PM8008_EN>;
|
||||
|
||||
vdd_l1_l2-supply = <&S3A>;
|
||||
|
||||
L1P: qcom,pm8008-l1@4000 {
|
||||
reg = <0x4000>;
|
||||
regulator-name = "pm8008_l1";
|
||||
regulator-min-microvolt = <528000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
qcom,min-dropout-voltage = <75000>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
|
||||
L2P: qcom,pm8008-l2@4100 {
|
||||
reg = <0x4100>;
|
||||
regulator-name = "pm8008_l2";
|
||||
regulator-min-microvolt = <528000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
qcom,min-dropout-voltage = <187500>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
|
||||
L3P: qcom,pm8008-l3@4200 {
|
||||
reg = <0x4200>;
|
||||
regulator-name = "pm8008_l3";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2896000>;
|
||||
qcom,min-dropout-voltage = <200000>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
|
||||
L4P: qcom,pm8008-l4@4300 {
|
||||
reg = <0x4300>;
|
||||
regulator-name = "pm8008_l4";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2896000>;
|
||||
qcom,min-dropout-voltage = <200000>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
|
||||
L5P: qcom,pm8008-l5@4400 {
|
||||
reg = <0x4400>;
|
||||
regulator-name = "pm8008_l5";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2896000>;
|
||||
qcom,min-dropout-voltage = <300000>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
|
||||
L6P: qcom,pm8008-l6@4500 {
|
||||
reg = <0x4500>;
|
||||
regulator-name = "pm8008_l6";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2896000>;
|
||||
qcom,min-dropout-voltage = <300000>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
|
||||
L7P: qcom,pm8008-l7@4600 {
|
||||
reg = <0x4600>;
|
||||
regulator-name = "pm8008_l7";
|
||||
regulator-min-microvolt = <1656000>;
|
||||
regulator-max-microvolt = <1896000>;
|
||||
qcom,min-dropout-voltage = <300000>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
&pm8008_regulators {
|
||||
vdd_l1_l2-supply = <&S3A>;
|
||||
};
|
||||
|
||||
&gcc_camss_top_gdsc {
|
||||
|
|
|
|||
Loading…
Reference in a new issue