diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 4a6560e19a71..f3d6b6ccdb9b 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -1412,6 +1412,12 @@ static int adreno_bind(struct device *dev)
 	if (adreno_support_64bit(adreno_dev))
 		kgsl_mmu_set_feature(device, KGSL_MMU_64BIT);
 
+	/*
+	 * Set the SMMU aperture on A6XX targets to use per-process pagetables.
+	 */
+	if (adreno_is_a6xx(adreno_dev))
+		kgsl_mmu_set_feature(device, KGSL_MMU_SMMU_APERTURE);
+
 	device->pwrctrl.bus_width = adreno_dev->gpucore->bus_width;
 
 	device->mmu.secured = (IS_ENABLED(CONFIG_QCOM_SECURE_BUFFER) &&
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index 2ce5060de820..2b19b6632b23 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -1084,13 +1084,15 @@ static int set_smmu_aperture(struct kgsl_device *device, int cb_num)
 {
 	int ret;
 
-	if (!qcom_scm_kgsl_set_smmu_aperture_available())
+	if (!test_bit(KGSL_MMU_SMMU_APERTURE, &device->mmu.features))
 		return 0;
 
 	ret = qcom_scm_kgsl_set_smmu_aperture(cb_num);
+	if (ret == -EBUSY)
+		ret = qcom_scm_kgsl_set_smmu_aperture(cb_num);
 
 	if (ret)
-		dev_err(device->dev, "Unable to set the SMMU aperture: %d\n",
+		dev_err(device->dev, "Unable to set the SMMU aperture: %d. The aperture needs to be set to use per-process pagetables\n",
 			ret);
 
 	return ret;
diff --git a/drivers/gpu/msm/kgsl_mmu.h b/drivers/gpu/msm/kgsl_mmu.h
index 27d3e5bb934d..8ce9c1ac228d 100644
--- a/drivers/gpu/msm/kgsl_mmu.h
+++ b/drivers/gpu/msm/kgsl_mmu.h
@@ -126,6 +126,8 @@ enum kgsl_mmu_feature {
 	KGSL_MMU_SECURE_CB_ALT,
 	/** @KGSL_MMU_LLC_ENABLE: Set if LLC is activated for the target */
 	KGSL_MMU_LLCC_ENABLE,
+	/** @KGSL_MMU_SMMU_APERTURE: Set the SMMU aperture */
+	KGSL_MMU_SMMU_APERTURE,
 };
 
 /**