mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 06:03:36 -04:00
Merge branch 'scsi-fixes'
This commit is contained in:
commit
87045b033a
497 changed files with 28001 additions and 2710 deletions
|
|
@ -117,10 +117,10 @@
|
|||
/* drbdsetup XY resize -d Z
|
||||
* you are free to reduce the device size to nothing, if you want to.
|
||||
* the upper limit with 64bit kernel, enough ram and flexible meta data
|
||||
* is 16 TB, currently. */
|
||||
* is 1 PiB, currently. */
|
||||
/* DRBD_MAX_SECTORS */
|
||||
#define DRBD_DISK_SIZE_SECT_MIN 0
|
||||
#define DRBD_DISK_SIZE_SECT_MAX (16 * (2LLU << 30))
|
||||
#define DRBD_DISK_SIZE_SECT_MAX (1 * (2LLU << 40))
|
||||
#define DRBD_DISK_SIZE_SECT_DEF 0 /* = disabled = no user size... */
|
||||
|
||||
#define DRBD_ON_IO_ERROR_DEF EP_PASS_ON
|
||||
|
|
|
|||
|
|
@ -204,6 +204,8 @@ extern bool __fscache_check_page_write(struct fscache_cookie *, struct page *);
|
|||
extern void __fscache_wait_on_page_write(struct fscache_cookie *, struct page *);
|
||||
extern bool __fscache_maybe_release_page(struct fscache_cookie *, struct page *,
|
||||
gfp_t);
|
||||
extern void __fscache_uncache_all_inode_pages(struct fscache_cookie *,
|
||||
struct inode *);
|
||||
|
||||
/**
|
||||
* fscache_register_netfs - Register a filesystem as desiring caching services
|
||||
|
|
@ -643,4 +645,23 @@ bool fscache_maybe_release_page(struct fscache_cookie *cookie,
|
|||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* fscache_uncache_all_inode_pages - Uncache all an inode's pages
|
||||
* @cookie: The cookie representing the inode's cache object.
|
||||
* @inode: The inode to uncache pages from.
|
||||
*
|
||||
* Uncache all the pages in an inode that are marked PG_fscache, assuming them
|
||||
* to be associated with the given cookie.
|
||||
*
|
||||
* This function may sleep. It will wait for pages that are being written out
|
||||
* and will wait whilst the PG_fscache mark is removed by the cache.
|
||||
*/
|
||||
static inline
|
||||
void fscache_uncache_all_inode_pages(struct fscache_cookie *cookie,
|
||||
struct inode *inode)
|
||||
{
|
||||
if (fscache_cookie_valid(cookie))
|
||||
__fscache_uncache_all_inode_pages(cookie, inode);
|
||||
}
|
||||
|
||||
#endif /* _LINUX_FSCACHE_H */
|
||||
|
|
|
|||
|
|
@ -24,12 +24,6 @@
|
|||
* See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
|
||||
*/
|
||||
#define MEM_ALLOC_THRESHOLD (1024*768*4+32)
|
||||
/* Minimum value that the pixel clock can be set to in pico seconds
|
||||
* This is determined by platform clock/3 where the minimum platform
|
||||
* clock is 533MHz. This gives 5629 pico seconds.
|
||||
*/
|
||||
#define MIN_PIX_CLK 5629
|
||||
#define MAX_PIX_CLK 96096
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -676,7 +676,8 @@ void irq_gc_mask_disable_reg(struct irq_data *d);
|
|||
void irq_gc_mask_set_bit(struct irq_data *d);
|
||||
void irq_gc_mask_clr_bit(struct irq_data *d);
|
||||
void irq_gc_unmask_enable_reg(struct irq_data *d);
|
||||
void irq_gc_ack(struct irq_data *d);
|
||||
void irq_gc_ack_set_bit(struct irq_data *d);
|
||||
void irq_gc_ack_clr_bit(struct irq_data *d);
|
||||
void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
|
||||
void irq_gc_eoi(struct irq_data *d);
|
||||
int irq_gc_set_wake(struct irq_data *d, unsigned int on);
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
#include <linux/compiler.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#define MIN_MEMORY_BLOCK_SIZE (1 << SECTION_SIZE_BITS)
|
||||
|
||||
struct memory_block {
|
||||
unsigned long start_section_nr;
|
||||
unsigned long end_section_nr;
|
||||
|
|
|
|||
|
|
@ -3,4 +3,11 @@
|
|||
struct ds1wm_driver_data {
|
||||
int active_high;
|
||||
int clock_rate;
|
||||
/* in milliseconds, the amount of time to */
|
||||
/* sleep following a reset pulse. Zero */
|
||||
/* should work if your bus devices recover*/
|
||||
/* time respects the 1-wire spec since the*/
|
||||
/* ds1wm implements the precise timings of*/
|
||||
/* a reset pulse/presence detect sequence.*/
|
||||
unsigned int reset_recover_delay;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,6 +64,19 @@ struct mmc_ext_csd {
|
|||
unsigned long long enhanced_area_offset; /* Units: Byte */
|
||||
unsigned int enhanced_area_size; /* Units: KB */
|
||||
unsigned int boot_size; /* in bytes */
|
||||
u8 raw_partition_support; /* 160 */
|
||||
u8 raw_erased_mem_count; /* 181 */
|
||||
u8 raw_ext_csd_structure; /* 194 */
|
||||
u8 raw_card_type; /* 196 */
|
||||
u8 raw_s_a_timeout; /* 217 */
|
||||
u8 raw_hc_erase_gap_size; /* 221 */
|
||||
u8 raw_erase_timeout_mult; /* 223 */
|
||||
u8 raw_hc_erase_grp_size; /* 224 */
|
||||
u8 raw_sec_trim_mult; /* 229 */
|
||||
u8 raw_sec_erase_mult; /* 230 */
|
||||
u8 raw_sec_feature_support;/* 231 */
|
||||
u8 raw_trim_mult; /* 232 */
|
||||
u8 raw_sectors[4]; /* 212 - 4 bytes */
|
||||
};
|
||||
|
||||
struct sd_scr {
|
||||
|
|
|
|||
|
|
@ -1097,12 +1097,6 @@ struct net_device {
|
|||
#define NETIF_F_ALL_FCOE (NETIF_F_FCOE_CRC | NETIF_F_FCOE_MTU | \
|
||||
NETIF_F_FSO)
|
||||
|
||||
#define NETIF_F_ALL_TX_OFFLOADS (NETIF_F_ALL_CSUM | NETIF_F_SG | \
|
||||
NETIF_F_FRAGLIST | NETIF_F_ALL_TSO | \
|
||||
NETIF_F_HIGHDMA | \
|
||||
NETIF_F_SCTP_CSUM | \
|
||||
NETIF_F_ALL_FCOE)
|
||||
|
||||
/*
|
||||
* If one device supports one of these features, then enable them
|
||||
* for all in netdev_increment_features.
|
||||
|
|
|
|||
|
|
@ -808,7 +808,7 @@ enum cpu_idle_type {
|
|||
* when BITS_PER_LONG <= 32 are pretty high and the returns do not justify the
|
||||
* increased costs.
|
||||
*/
|
||||
#if BITS_PER_LONG > 32
|
||||
#if 0 /* BITS_PER_LONG > 32 -- currently broken: it increases power usage under light load */
|
||||
# define SCHED_LOAD_RESOLUTION 10
|
||||
# define scale_load(w) ((w) << SCHED_LOAD_RESOLUTION)
|
||||
# define scale_load_down(w) ((w) >> SCHED_LOAD_RESOLUTION)
|
||||
|
|
@ -844,6 +844,7 @@ enum cpu_idle_type {
|
|||
#define SD_SERIALIZE 0x0400 /* Only a single load balancing instance */
|
||||
#define SD_ASYM_PACKING 0x0800 /* Place busy groups earlier in the domain */
|
||||
#define SD_PREFER_SIBLING 0x1000 /* Prefer to place tasks in a sibling domain */
|
||||
#define SD_OVERLAP 0x2000 /* sched_domains of this level overlap */
|
||||
|
||||
enum powersavings_balance_level {
|
||||
POWERSAVINGS_BALANCE_NONE = 0, /* No power saving load balance */
|
||||
|
|
@ -893,16 +894,21 @@ static inline int sd_power_saving_flags(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct sched_group {
|
||||
struct sched_group *next; /* Must be a circular list */
|
||||
struct sched_group_power {
|
||||
atomic_t ref;
|
||||
|
||||
/*
|
||||
* CPU power of this group, SCHED_LOAD_SCALE being max power for a
|
||||
* single CPU.
|
||||
*/
|
||||
unsigned int cpu_power, cpu_power_orig;
|
||||
unsigned int power, power_orig;
|
||||
};
|
||||
|
||||
struct sched_group {
|
||||
struct sched_group *next; /* Must be a circular list */
|
||||
atomic_t ref;
|
||||
|
||||
unsigned int group_weight;
|
||||
struct sched_group_power *sgp;
|
||||
|
||||
/*
|
||||
* The CPUs this group covers.
|
||||
|
|
@ -1254,6 +1260,9 @@ struct task_struct {
|
|||
#ifdef CONFIG_PREEMPT_RCU
|
||||
int rcu_read_lock_nesting;
|
||||
char rcu_read_unlock_special;
|
||||
#if defined(CONFIG_RCU_BOOST) && defined(CONFIG_TREE_PREEMPT_RCU)
|
||||
int rcu_boosted;
|
||||
#endif /* #if defined(CONFIG_RCU_BOOST) && defined(CONFIG_TREE_PREEMPT_RCU) */
|
||||
struct list_head rcu_node_entry;
|
||||
#endif /* #ifdef CONFIG_PREEMPT_RCU */
|
||||
#ifdef CONFIG_TREE_PREEMPT_RCU
|
||||
|
|
|
|||
|
|
@ -112,11 +112,7 @@ struct sdla_dlci_conf {
|
|||
short Tb_max;
|
||||
};
|
||||
|
||||
#ifndef __KERNEL__
|
||||
|
||||
void sdla(void *cfg_info, char *dev, struct frad_conf *conf, int quiet);
|
||||
|
||||
#else
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/* important Z80 window addresses */
|
||||
#define SDLA_CONTROL_WND 0xE000
|
||||
|
|
|
|||
Loading…
Reference in a new issue