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msm: kgsl: Update A635 GPU revision number

Browse source 
A635 GPU correct revision number is A642L. Update the
revision and revision checks to reflect correct value.

Change-Id: I92a856cdf8775354216ffa64f6f1fdd86346daf2
Signed-off-by: Pankaj Gupta <gpankaj@codeaurora.org>
This commit is contained in:
Pankaj Gupta 2021-05-13 19:21:31 +05:30 • committed by Gerrit - the friendly Code Review server
commit 871cd6e975
4 changed files with 23 additions and 17 deletions
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7
drivers/gpu/msm/adreno-gpulist.h
View file

@ -1713,9 +1713,10 @@ static const struct adreno_a6xx_core adreno_gpu_core_a642 = {
.ctxt_record_size = 2496 * 1024,
};
static const struct adreno_a6xx_core adreno_gpu_core_a635 = {
static const struct adreno_a6xx_core adreno_gpu_core_a642l = {
.base = {
DEFINE_ADRENO_REV(ADRENO_REV_A635, 6, 3, 5, ANY_ID),
DEFINE_ADRENO_REV(ADRENO_REV_A642, ANY_ID, ANY_ID, ANY_ID, ANY_ID),
.compatible = "qcom,adreno-gpu-a642l",
.features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV |
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
ADRENO_PREEMPTION | ADRENO_IFPC | ADRENO_BCL,
@ -1850,7 +1851,6 @@ static const struct adreno_gpu_core *adreno_gpulist[] = {
&adreno_gpu_core_a619.base,
&adreno_gpu_core_a619_variant.base,
&adreno_gpu_core_a620.base,
&adreno_gpu_core_a635.base,
&adreno_gpu_core_a640.base,
&adreno_gpu_core_a650.base,
&adreno_gpu_core_a650v2.base,
@ -1861,5 +1861,6 @@ static const struct adreno_gpu_core *adreno_gpulist[] = {
&adreno_gpu_core_a616.base,
&adreno_gpu_core_a610.base,
&adreno_gpu_core_a642.base,
&adreno_gpu_core_a642l.base,
&adreno_gpu_core_a702.base,
};

21
drivers/gpu/msm/adreno.h
View file

@ -200,7 +200,6 @@ enum adreno_gpurev {
ADRENO_REV_A619 = 619,
ADRENO_REV_A620 = 620,
ADRENO_REV_A630 = 630,
ADRENO_REV_A635 = 635,
ADRENO_REV_A640 = 640,
ADRENO_REV_A642 = 642,
ADRENO_REV_A650 = 650,
@ -1061,25 +1060,31 @@ static inline int adreno_is_a642(struct adreno_device *adreno_dev)
"qcom,adreno-gpu-a642"));
}
static inline int adreno_is_a642l(struct adreno_device *adreno_dev)
{
return (adreno_dev->gpucore->compatible &&
!strcmp(adreno_dev->gpucore->compatible,
"qcom,adreno-gpu-a642l"));
}
ADRENO_TARGET(a610, ADRENO_REV_A610)
ADRENO_TARGET(a612, ADRENO_REV_A612)
ADRENO_TARGET(a618, ADRENO_REV_A618)
ADRENO_TARGET(a619, ADRENO_REV_A619)
ADRENO_TARGET(a620, ADRENO_REV_A620)
ADRENO_TARGET(a630, ADRENO_REV_A630)
ADRENO_TARGET(a635, ADRENO_REV_A635)
ADRENO_TARGET(a640, ADRENO_REV_A640)
ADRENO_TARGET(a650, ADRENO_REV_A650)
ADRENO_TARGET(a680, ADRENO_REV_A680)
ADRENO_TARGET(a702, ADRENO_REV_A702)
/* A635 and A642 are derived from A660 and shares same logic */
/* A642 and A642L are derived from A660 and shares same logic */
static inline int adreno_is_a660(struct adreno_device *adreno_dev)
{
unsigned int rev = ADRENO_GPUREV(adreno_dev);
return (rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635 ||
adreno_is_a642(adreno_dev));
return (rev == ADRENO_REV_A660 || adreno_is_a642(adreno_dev) ||
adreno_is_a642l(adreno_dev));
}
/*
@ -1109,7 +1114,7 @@ static inline int adreno_is_a640_family(struct adreno_device *adreno_dev)
* Derived GPUs from A650 needs to be added to this list.
* A650 is derived from A640 but register specs has been
* changed hence do not belongs to A640 family. A620, A642,
* A660, A690 follows the register specs of A650.
* A642L, A660, A690 follows the register specs of A650.
*
*/
static inline int adreno_is_a650_family(struct adreno_device *adreno_dev)
@ -1117,8 +1122,8 @@ static inline int adreno_is_a650_family(struct adreno_device *adreno_dev)
unsigned int rev = ADRENO_GPUREV(adreno_dev);
return (rev == ADRENO_REV_A650 || rev == ADRENO_REV_A620 ||
rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635 ||
adreno_is_a642(adreno_dev));
rev == ADRENO_REV_A660 || adreno_is_a642(adreno_dev) ||
adreno_is_a642l(adreno_dev));
}
static inline int adreno_is_a619_holi(struct adreno_device *adreno_dev)

10
drivers/gpu/msm/adreno_a6xx.c
View file

@ -92,7 +92,7 @@ static u32 a6xx_ifpc_pwrup_reglist[] = {
A6XX_CP_AHB_CNTL,
};
/* Applicable to a620, a635, a650 and a660 */
/* Applicable to a620, a642l, a650 and a660 */
static u32 a650_pwrup_reglist[] = {
A6XX_CP_PROTECT_REG + 47, /* Programmed for infinite span */
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
@ -175,7 +175,7 @@ int a6xx_init(struct adreno_device *adreno_dev)
/* If the memory type is DDR 4, override the existing configuration */
if (of_fdt_get_ddrtype() == 0x7) {
if (adreno_is_a642(adreno_dev) ||
adreno_is_a635(adreno_dev))
adreno_is_a642l(adreno_dev))
adreno_dev->highest_bank_bit = 14;
else if ((adreno_is_a650(adreno_dev) ||
adreno_is_a660(adreno_dev)))
@ -632,7 +632,7 @@ void a6xx_start(struct adreno_device *adreno_dev)
kgsl_regwrite(device, A6XX_UCHE_CACHE_WAYS, 0x4);
/* ROQ sizes are twice as big on a640/a680 than on a630 */
if ((ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A635) &&
if ((ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640) &&
!adreno_is_a702(adreno_dev)) {
kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
@ -818,8 +818,8 @@ void a6xx_start(struct adreno_device *adreno_dev)
kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1);
kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
/* Set dualQ + disable afull for A660 GPU but not for A635 */
if (!adreno_is_a635(adreno_dev))
/* Set dualQ + disable afull for A660, A642 GPU but not for A642L */
if (!adreno_is_a642l(adreno_dev))
kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x66906);
}

2
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -1997,7 +1997,7 @@ static bool a6xx_gmu_scales_bandwidth(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
return (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A635);
return (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640);
}
static irqreturn_t a6xx_gmu_irq_handler(int irq, void *data)