From fe699a2f55af1cd6ad4514feb46da35e2c2871a5 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Wed, 25 Nov 2020 17:57:59 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Add dtsi nodes for i2c, spi and hsuart Add dtsi nodes for i2c, spi and hsuart for sdxnightjar. Change-Id: Ic0c755c7642111aabc13b11bb05516244cd2e096 --- qcom/sdxnightjar-blsp.dtsi | 385 +++++++++++++++++++++++++++++++++++++ 1 file changed, 385 insertions(+) create mode 100644 qcom/sdxnightjar-blsp.dtsi diff --git a/qcom/sdxnightjar-blsp.dtsi b/qcom/sdxnightjar-blsp.dtsi new file mode 100644 index 000000000000..f6950a0c4149 --- /dev/null +++ b/qcom/sdxnightjar-blsp.dtsi @@ -0,0 +1,385 @@ +#include "sdxnightjar-pinctrl.dtsi" + +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; +}; + +&soc { + dma_blsp1: qcom,sps-dma@0x7884000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x23000>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@78b5000 { /* BLSP1 QUP1 gpios 2,3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b5000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@78B6000 { /* BLSP1 QUP2 gpios 6,7 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78B6000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@78B7000 { /* BLSP1 QUP3 gpios 10, 11 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78B7000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@78B8000 { /* BLSP1 QUP4 gpios 14, 15 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78B8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + spi_1: spi@78B5000 { /* BLSP1 QUP1 gpios 0, 1, 2, 3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x078B5000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>; + status = "disabled"; + }; + + spi_2: spi@78B6000 { /* BLSP1 QUP2 gpios 4, 5, 6, 7 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78B6000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + status = "disabled"; + }; + + spi_3: spi@78B7000 { /* BLSP1 QUP3 gpios 8, 9, 10, 11 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x078B7000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; + status = "disabled"; + }; + + spi_4: spi@78B8000 { /* BLSP1 QUP4 gpios 16, 17, 18, 19 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x078B8000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; + status = "disabled"; + }; + + blsp1_uart1_hs: uart@78AF000 { /* BLSP1 UART1 gpios 0, 1, 2, 3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78AF000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 107 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 1 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart2_hs: uart@78B0000 { /* BLSP1 UART2 gpios 4, 5, 6, 7 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B0000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 108 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 5 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@78B1000 { /* BLSP1 UART3 gpios 8, 9, 10, 11 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B1000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 109 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 9 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_sleep>; + pinctrl-1 = <&blsp1_uart3_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart4a_hs: uarta@78B2000 { /* BLSP1 UART4 gpios 12, 13, 14, 15*/ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B2000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 110 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 13 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4_sleep>; + pinctrl-1 = <&blsp1_uart4_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart4b_hs: uartb@78B2000 { /* BLSP1 UART4b gpios 16, 17, 18, 19*/ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B2000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 110 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 17 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4b_sleep>; + pinctrl-1 = <&blsp1_uart4b_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; +}; From eeea692d512bb4210afa393ffbae03a76cebc8b9 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 8 Dec 2020 23:11:39 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Rectify all BLSP QUP nodes with correct clocks This change corrects clock nodes for each QUP instance for sdxnightjar. Also correct the interconnect end points for each BLSP QUP instance. Change-Id: I3b3c85b82c23b0e103a2ac11b8c009593dda586a --- qcom/sdxnightjar-blsp.dtsi | 78 +++++++++++++++++++------------------- qcom/sdxnightjar.dtsi | 1 + 2 files changed, 40 insertions(+), 39 deletions(-) diff --git a/qcom/sdxnightjar-blsp.dtsi b/qcom/sdxnightjar-blsp.dtsi index f6950a0c4149..6fa8b09ba546 100644 --- a/qcom/sdxnightjar-blsp.dtsi +++ b/qcom/sdxnightjar-blsp.dtsi @@ -33,12 +33,12 @@ dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_1_active>; pinctrl-1 = <&i2c_1_sleep>; @@ -56,12 +56,12 @@ dmas = <&dma_blsp1 10 64 0x20000020 0x20>, <&dma_blsp1 11 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; @@ -79,12 +79,12 @@ dmas = <&dma_blsp1 12 64 0x20000020 0x20>, <&dma_blsp1 13 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; @@ -102,12 +102,12 @@ dmas = <&dma_blsp1 14 64 0x20000020 0x20>, <&dma_blsp1 15 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_4_active>; pinctrl-1 = <&i2c_4_sleep>; @@ -129,14 +129,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <8>; qcom,bam-producer-pipe-index = <9>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_1_active>; pinctrl-1 = <&spi_1_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; status = "disabled"; }; @@ -155,14 +155,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <10>; qcom,bam-producer-pipe-index = <11>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_2_active>; pinctrl-1 = <&spi_2_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; status = "disabled"; }; @@ -181,14 +181,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <12>; qcom,bam-producer-pipe-index = <13>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_3_active>; pinctrl-1 = <&spi_3_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; status = "disabled"; }; @@ -207,14 +207,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <14>; qcom,bam-producer-pipe-index = <15>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_4_active>; pinctrl-1 = <&spi_4_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; status = "disabled"; }; @@ -240,14 +240,14 @@ qcom,bam-rx-ep-pipe-index = <1>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart1_sleep>; pinctrl-1 = <&blsp1_uart1_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -273,14 +273,14 @@ qcom,bam-rx-ep-pipe-index = <3>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2_sleep>; pinctrl-1 = <&blsp1_uart2_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -306,14 +306,14 @@ qcom,bam-rx-ep-pipe-index = <5>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_sleep>; pinctrl-1 = <&blsp1_uart3_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -339,14 +339,14 @@ qcom,bam-rx-ep-pipe-index = <7>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4_sleep>; pinctrl-1 = <&blsp1_uart4_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -372,14 +372,14 @@ qcom,bam-rx-ep-pipe-index = <7>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4b_sleep>; pinctrl-1 = <&blsp1_uart4b_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8337f22edeb9..033cddbd138e 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -713,3 +713,4 @@ #include "sdxnightjar-regulator.dtsi" #include "sdxnightjar-usb.dtsi" #include "sdxnightjar-pinctrl.dtsi" +#include "sdxnightjar-blsp.dtsi"