Samsung 3rd clock updates for 3.16

- add clock for new exynos5410 SoC
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJTiNPgAAoJEA0Cl+kVi2xq7ooQAJayfGs1cdggE10OfbGImzsO
 m+GNFnHxvr+L4M5aZpwpTBcm5I0QZZghw7Ey/hdF+rErhZVj/xQjun8eri/o9vLz
 Bs/prI26ZjjvuyEY8gLMhh4FADorB3KfTFbAfSFTiN3TyNZRuFCb3ZQoTOIf0Pwb
 KVsNmn9EnqrqWPvtvqFXHuo6FVV9MvBGYs86fTfbYc+d3jQHebgVu19vZSHKo3EV
 Bm00h8SvrnkNiOYZ1Cz2VnFLx5d50+tNyYWgJyv1WvuorbVgY6sXlob5coJhFHBM
 7Wdn3OUFRwXVZpd1+5RtQcbm7UPIu/pkK5we3isJHIt4T2GJeExuROTvIQ39VX8E
 xHFOu8jkISvW61c/T9Je9MfWI4RfdVk3qktkdRclWMn4lB3GovbMZulIWe5Ue1n4
 hw+w00Jpuw0tdZO18Cls+Grz1ZoSLoRKB+kDSudLXiG4CqG5Hqk5yZeq13zxes1E
 9Ia6XVQ+gRJvuwj+qZHzfQhlpQ+gwtxYSrF6uN8Ehr2z7+sYOq8GNW9yp9EjcsOj
 wfdjNC9zogOGyhNFk7UaLsFHo77c5ToU1UfA1yo2PLAuk00HX2K8zM/iJA3TzZmi
 JiwoML6/iQ6Pc1i+GGTnoQs8mu4nEhNZ+3Q8UoY7exdK60uENsOlR2P+HJCig89y
 6IbEzdWOGkGQQJn8XAMx
 =mhiW
 -----END PGP SIGNATURE-----

Merge tag 'samsung-clk-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Merge "Samsung 3rd clock updates for 3.16" from Kukjin Kim:

- add clock for new exynos5410 SoC

* tag 'samsung-clk-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  clk: exynos5410: register clocks using common clock framework

Signed-off-by: Olof Johansson <[email protected]>

Documentation/devicetree/bindings/clock/exynos5410-clock.txt

@@ -0,0 +1,45 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It
+is expected that it is defined using standard clock bindings
+with following clock-output-name:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Example 1: An example of a clock controller node is listed below.
+
+	clock: clock-controller@0x10010000 {
+		compatible = "samsung,exynos5410-clock";
+		reg = <0x10010000 0x30000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the clock
+	   controller. Refer to the standard clock bindings for information
+	   about 'clocks' and 'clock-names' property.
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+	};