From 87c965206af68aa0797932dbfb3ab176b7dcac41 Mon Sep 17 00:00:00 2001
From: Deepak Kumar <dkumar@qti.qualcomm.com>
Date: Thu, 20 Aug 2020 12:36:09 +0530
Subject: [PATCH] ARM: dts: qcom: Add clocks to access KGSL SMMU register space

Add GPU_CC_CX_GMU_CLK, GPU_CC_HUB_AON_CLK and GPU_CC_HUB_CX_INT_CLK
clock to the list of clocks to vote for in order to access the KGSL
SMMU register space.

Change-Id: If23b108f6d22f5b6903c4962108fd273832063df
---
 qcom/shima-gpu.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi
index db2ebcd2e135..924fb43d6ad7 100644
--- a/qcom/shima-gpu.dtsi
+++ b/qcom/shima-gpu.dtsi
@@ -28,13 +28,19 @@
 			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
 			<&gpucc GPU_CC_AHB_CLK>,
 			<&aopcc QDSS_CLK>,
-			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+			<&gpucc GPU_CC_CX_GMU_CLK>,
+			<&gpucc GPU_CC_HUB_AON_CLK>,
+			<&gpucc GPU_CC_HUB_CX_INT_CLK>;
 
 		clock-names = "gcc_gpu_memnoc_gfx",
 				"gcc_gpu_snoc_dvm_gfx",
 				"gpu_cc_ahb",
 				"apb_pclk",
-				"gpu_cc_hlos1_vote_gpu_smmu_clk";
+				"gpu_cc_hlos1_vote_gpu_smmu_clk",
+				"gpu_cc_cx_gmu",
+				"gpu_cc_hub_aon",
+				"gpu_cc_hub_cx_int";
 
 		qcom,chipid = <0x06060001>;