mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
ARM updates for 5.4-rc1:
- fix various clang build and cppcheck issues - switch ARM to use new common outgoing-CPU-notification code - add some additional explanation about the boot code - kbuild "make clean" fixes - get rid of another "(____ptrval____)", this time for the VDSO code - avoid treating cache maintenance faults as a write - add a frame pointer unwinder implementation for clang - add EDAC support for Aurora L2 cache - improve robustness of adjust_lowmem_bounds() finding the bounds of lowmem. - add reset control for AMBA primecell devices -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAXYZCdvTnkBvkraxkAQK7vQ//UO0XJ1InSLnWzPYuNwJGcCmzHIg6p40A VxnvDTVxZH6UKDhBg8xx+gpPOhwZElGyc0H563p5jgmjzbIesESS5Xy3hUUMkQ9y A6Ta9Nk+NhL+j9O9VtcOk90oQJsLuVyYtHTfk6Wl9xaVLjM1OALWNzCSDqXIPTjF qEhTRahlv9Nc9aisFJAPduf/zQx9ULaZVvDzTo6clXSD7ieSy0MZRiRbcH3MJwiY Q5AbImF49NGcNtlknPh8Gnz/4P3q+bxQDmrzki9d4Fcy2brko845q9Ca5PC+iXro fZHvs8q2+8xz4PuOddBrYebqPIIv+3W6uPlJAPjO0MQrxPTUxRBxqAkYXxwTZBx/ A79AQsbnmUSyOV4EI2lk9USmN/GF2QwGOusRoiA/XMbSVfqnVZWH5mE98dr+2vn+ rUnTq9yvSz2y6QH7+UI+7Q7T8jg4QFBBmPDfCP+yTOWqPb8u070h+VgLBr28g1JL t6VtzOeI4wyl7E/WInmoM/d8SXnjv/1yNzLBcCdvgBV94fUQAV5EP+cDGJ0hv1SJ TGywm8adf3zAa7ZUAOhBoAK3gkNqjJB28ynsH4QmBUmsKkozxoKwwb4jjbGgcoUY rYII4VyoQB/0eX5/i8u69krA+3QNRhehLWC/zM4ZK5lKfFRCnNDvLgiIEM5b59JW nBywRtpyw2I= =Evmc -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm Pull ARM updates from Russell King: - fix various clang build and cppcheck issues - switch ARM to use new common outgoing-CPU-notification code - add some additional explanation about the boot code - kbuild "make clean" fixes - get rid of another "(____ptrval____)", this time for the VDSO code - avoid treating cache maintenance faults as a write - add a frame pointer unwinder implementation for clang - add EDAC support for Aurora L2 cache - improve robustness of adjust_lowmem_bounds() finding the bounds of lowmem. - add reset control for AMBA primecell devices * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (24 commits) ARM: 8906/1: drivers/amba: add reset control to amba bus probe ARM: 8905/1: Emit __gnu_mcount_nc when using Clang 10.0.0 or newer ARM: 8904/1: skip nomap memblocks while finding the lowmem/highmem boundary ARM: 8903/1: ensure that usable memory in bank 0 starts from a PMD-aligned address ARM: 8891/1: EDAC: armada_xp: Add support for more SoCs ARM: 8888/1: EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC ARM: 8892/1: EDAC: Add missing debugfs_create_x32 wrapper ARM: 8890/1: l2x0: add marvell,ecc-enable property for aurora ARM: 8889/1: dt-bindings: document marvell,ecc-enable binding ARM: 8886/1: l2x0: support parity-enable/disable on aurora ARM: 8885/1: aurora-l2: add defines for parity and ECC registers ARM: 8887/1: aurora-l2: add prefix to MAX_RANGE_SIZE ARM: 8902/1: l2c: move cache-aurora-l2.h to asm/hardware ARM: 8900/1: UNWINDER_FRAME_POINTER implementation for Clang ARM: 8898/1: mm: Don't treat faults reported from cache maintenance as writes ARM: 8896/1: VDSO: Don't leak kernel addresses ARM: 8895/1: visit mach-* and plat-* directories when cleaning ARM: 8894/1: boot: Replace open-coded nop with macro ARM: 8893/1: boot: Explain the 8 nops ARM: 8876/1: fix O= building with CONFIG_FPE_FASTFPE ...
This commit is contained in:
Linus Torvalds
commit
8808cf8cbc
21 changed files with 1027 additions and 24 deletions
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@ -466,6 +466,13 @@ config EDAC_SIFIVE
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help
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Support for error detection and correction on the SiFive SoCs.
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config EDAC_ARMADA_XP
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bool "Marvell Armada XP DDR and L2 Cache ECC"
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depends on MACH_MVEBU_V7
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help
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Support for error correction and detection on the Marvell Aramada XP
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DDR RAM and L2 cache controllers.
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config EDAC_SYNOPSYS
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tristate "Synopsys DDR Memory Controller"
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depends on ARCH_ZYNQ || ARCH_ZYNQMP
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@ -80,6 +80,7 @@ obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o
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obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o
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obj-$(CONFIG_EDAC_SIFIVE) += sifive_edac.o
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obj-$(CONFIG_EDAC_ARMADA_XP) += armada_xp_edac.o
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obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
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obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
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obj-$(CONFIG_EDAC_TI) += ti_edac.o
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635
drivers/edac/armada_xp_edac.c
Normal file
635
drivers/edac/armada_xp_edac.c
Normal file
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@ -0,0 +1,635 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Pengutronix, Jan Luebbe <kernel@pengutronix.de>
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*/
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#include <linux/kernel.h>
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#include <linux/edac.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/cache-aurora-l2.h>
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#include "edac_mc.h"
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#include "edac_device.h"
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#include "edac_module.h"
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/************************ EDAC MC (DDR RAM) ********************************/
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#define SDRAM_NUM_CS 4
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#define SDRAM_CONFIG_REG 0x0
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#define SDRAM_CONFIG_ECC_MASK BIT(18)
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#define SDRAM_CONFIG_REGISTERED_MASK BIT(17)
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#define SDRAM_CONFIG_BUS_WIDTH_MASK BIT(15)
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#define SDRAM_ADDR_CTRL_REG 0x10
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#define SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs) (20+cs)
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#define SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(cs) (0x1 << SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs))
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#define SDRAM_ADDR_CTRL_ADDR_SEL_MASK(cs) BIT(16+cs)
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#define SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs) (cs*4+2)
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#define SDRAM_ADDR_CTRL_SIZE_LOW_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs))
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#define SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs) (cs*4)
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#define SDRAM_ADDR_CTRL_STRUCT_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs))
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#define SDRAM_ERR_DATA_H_REG 0x40
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#define SDRAM_ERR_DATA_L_REG 0x44
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#define SDRAM_ERR_RECV_ECC_REG 0x48
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#define SDRAM_ERR_RECV_ECC_VALUE_MASK 0xff
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#define SDRAM_ERR_CALC_ECC_REG 0x4c
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#define SDRAM_ERR_CALC_ECC_ROW_OFFSET 8
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#define SDRAM_ERR_CALC_ECC_ROW_MASK (0xffff << SDRAM_ERR_CALC_ECC_ROW_OFFSET)
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#define SDRAM_ERR_CALC_ECC_VALUE_MASK 0xff
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#define SDRAM_ERR_ADDR_REG 0x50
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#define SDRAM_ERR_ADDR_BANK_OFFSET 23
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#define SDRAM_ERR_ADDR_BANK_MASK (0x7 << SDRAM_ERR_ADDR_BANK_OFFSET)
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#define SDRAM_ERR_ADDR_COL_OFFSET 8
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#define SDRAM_ERR_ADDR_COL_MASK (0x7fff << SDRAM_ERR_ADDR_COL_OFFSET)
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#define SDRAM_ERR_ADDR_CS_OFFSET 1
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#define SDRAM_ERR_ADDR_CS_MASK (0x3 << SDRAM_ERR_ADDR_CS_OFFSET)
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#define SDRAM_ERR_ADDR_TYPE_MASK BIT(0)
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#define SDRAM_ERR_CTRL_REG 0x54
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#define SDRAM_ERR_CTRL_THR_OFFSET 16
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#define SDRAM_ERR_CTRL_THR_MASK (0xff << SDRAM_ERR_CTRL_THR_OFFSET)
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#define SDRAM_ERR_CTRL_PROP_MASK BIT(9)
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#define SDRAM_ERR_SBE_COUNT_REG 0x58
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#define SDRAM_ERR_DBE_COUNT_REG 0x5c
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#define SDRAM_ERR_CAUSE_ERR_REG 0xd0
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#define SDRAM_ERR_CAUSE_MSG_REG 0xd8
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#define SDRAM_ERR_CAUSE_DBE_MASK BIT(1)
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#define SDRAM_ERR_CAUSE_SBE_MASK BIT(0)
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#define SDRAM_RANK_CTRL_REG 0x1e0
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#define SDRAM_RANK_CTRL_EXIST_MASK(cs) BIT(cs)
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struct axp_mc_drvdata {
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void __iomem *base;
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/* width in bytes */
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unsigned int width;
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/* bank interleaving */
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bool cs_addr_sel[SDRAM_NUM_CS];
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char msg[128];
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};
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/* derived from "DRAM Address Multiplexing" in the ARAMDA XP Functional Spec */
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static uint32_t axp_mc_calc_address(struct axp_mc_drvdata *drvdata,
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uint8_t cs, uint8_t bank, uint16_t row,
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uint16_t col)
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{
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if (drvdata->width == 8) {
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/* 64 bit */
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if (drvdata->cs_addr_sel[cs])
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/* bank interleaved */
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return (((row & 0xfff8) << 16) |
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((bank & 0x7) << 16) |
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((row & 0x7) << 13) |
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((col & 0x3ff) << 3));
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else
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return (((row & 0xffff << 16) |
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((bank & 0x7) << 13) |
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((col & 0x3ff)) << 3));
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} else if (drvdata->width == 4) {
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/* 32 bit */
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if (drvdata->cs_addr_sel[cs])
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/* bank interleaved */
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return (((row & 0xfff0) << 15) |
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((bank & 0x7) << 16) |
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((row & 0xf) << 12) |
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((col & 0x3ff) << 2));
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else
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return (((row & 0xffff << 15) |
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((bank & 0x7) << 12) |
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((col & 0x3ff)) << 2));
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} else {
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/* 16 bit */
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if (drvdata->cs_addr_sel[cs])
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/* bank interleaved */
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return (((row & 0xffe0) << 14) |
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((bank & 0x7) << 16) |
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((row & 0x1f) << 11) |
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((col & 0x3ff) << 1));
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else
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return (((row & 0xffff << 14) |
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((bank & 0x7) << 11) |
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((col & 0x3ff)) << 1));
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}
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}
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static void axp_mc_check(struct mem_ctl_info *mci)
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{
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struct axp_mc_drvdata *drvdata = mci->pvt_info;
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uint32_t data_h, data_l, recv_ecc, calc_ecc, addr;
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uint32_t cnt_sbe, cnt_dbe, cause_err, cause_msg;
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uint32_t row_val, col_val, bank_val, addr_val;
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uint8_t syndrome_val, cs_val;
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char *msg = drvdata->msg;
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data_h = readl(drvdata->base + SDRAM_ERR_DATA_H_REG);
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data_l = readl(drvdata->base + SDRAM_ERR_DATA_L_REG);
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recv_ecc = readl(drvdata->base + SDRAM_ERR_RECV_ECC_REG);
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calc_ecc = readl(drvdata->base + SDRAM_ERR_CALC_ECC_REG);
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addr = readl(drvdata->base + SDRAM_ERR_ADDR_REG);
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cnt_sbe = readl(drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
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cnt_dbe = readl(drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
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cause_err = readl(drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
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cause_msg = readl(drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
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/* clear cause registers */
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writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
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drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
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writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
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drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
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/* clear error counter registers */
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if (cnt_sbe)
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writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
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if (cnt_dbe)
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writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
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if (!cnt_sbe && !cnt_dbe)
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return;
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if (!(addr & SDRAM_ERR_ADDR_TYPE_MASK)) {
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if (cnt_sbe)
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cnt_sbe--;
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else
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dev_warn(mci->pdev, "inconsistent SBE count detected");
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} else {
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if (cnt_dbe)
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cnt_dbe--;
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else
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dev_warn(mci->pdev, "inconsistent DBE count detected");
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}
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/* report earlier errors */
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if (cnt_sbe)
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
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cnt_sbe, /* error count */
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0, 0, 0, /* pfn, offset, syndrome */
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-1, -1, -1, /* top, mid, low layer */
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mci->ctl_name,
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"details unavailable (multiple errors)");
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if (cnt_dbe)
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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cnt_sbe, /* error count */
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0, 0, 0, /* pfn, offset, syndrome */
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-1, -1, -1, /* top, mid, low layer */
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mci->ctl_name,
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"details unavailable (multiple errors)");
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/* report details for most recent error */
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cs_val = (addr & SDRAM_ERR_ADDR_CS_MASK) >> SDRAM_ERR_ADDR_CS_OFFSET;
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bank_val = (addr & SDRAM_ERR_ADDR_BANK_MASK) >> SDRAM_ERR_ADDR_BANK_OFFSET;
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row_val = (calc_ecc & SDRAM_ERR_CALC_ECC_ROW_MASK) >> SDRAM_ERR_CALC_ECC_ROW_OFFSET;
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col_val = (addr & SDRAM_ERR_ADDR_COL_MASK) >> SDRAM_ERR_ADDR_COL_OFFSET;
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syndrome_val = (recv_ecc ^ calc_ecc) & 0xff;
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addr_val = axp_mc_calc_address(drvdata, cs_val, bank_val, row_val,
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col_val);
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msg += sprintf(msg, "row=0x%04x ", row_val); /* 11 chars */
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msg += sprintf(msg, "bank=0x%x ", bank_val); /* 9 chars */
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msg += sprintf(msg, "col=0x%04x ", col_val); /* 11 chars */
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msg += sprintf(msg, "cs=%d", cs_val); /* 4 chars */
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if (!(addr & SDRAM_ERR_ADDR_TYPE_MASK)) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
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1, /* error count */
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addr_val >> PAGE_SHIFT,
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addr_val & ~PAGE_MASK,
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syndrome_val,
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cs_val, -1, -1, /* top, mid, low layer */
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mci->ctl_name, drvdata->msg);
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} else {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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1, /* error count */
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addr_val >> PAGE_SHIFT,
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addr_val & ~PAGE_MASK,
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syndrome_val,
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cs_val, -1, -1, /* top, mid, low layer */
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mci->ctl_name, drvdata->msg);
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}
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}
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static void axp_mc_read_config(struct mem_ctl_info *mci)
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{
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struct axp_mc_drvdata *drvdata = mci->pvt_info;
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uint32_t config, addr_ctrl, rank_ctrl;
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unsigned int i, cs_struct, cs_size;
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struct dimm_info *dimm;
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config = readl(drvdata->base + SDRAM_CONFIG_REG);
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if (config & SDRAM_CONFIG_BUS_WIDTH_MASK)
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/* 64 bit */
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drvdata->width = 8;
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else
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/* 32 bit */
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drvdata->width = 4;
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addr_ctrl = readl(drvdata->base + SDRAM_ADDR_CTRL_REG);
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rank_ctrl = readl(drvdata->base + SDRAM_RANK_CTRL_REG);
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for (i = 0; i < SDRAM_NUM_CS; i++) {
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dimm = mci->dimms[i];
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if (!(rank_ctrl & SDRAM_RANK_CTRL_EXIST_MASK(i)))
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continue;
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drvdata->cs_addr_sel[i] =
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!!(addr_ctrl & SDRAM_ADDR_CTRL_ADDR_SEL_MASK(i));
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cs_struct = (addr_ctrl & SDRAM_ADDR_CTRL_STRUCT_MASK(i)) >> SDRAM_ADDR_CTRL_STRUCT_OFFSET(i);
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cs_size = ((addr_ctrl & SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(i)) >> (SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(i) - 2) |
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((addr_ctrl & SDRAM_ADDR_CTRL_SIZE_LOW_MASK(i)) >> SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(i)));
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switch (cs_size) {
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case 0: /* 2GBit */
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dimm->nr_pages = 524288;
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break;
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case 1: /* 256MBit */
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dimm->nr_pages = 65536;
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break;
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case 2: /* 512MBit */
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dimm->nr_pages = 131072;
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break;
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case 3: /* 1GBit */
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dimm->nr_pages = 262144;
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break;
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case 4: /* 4GBit */
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dimm->nr_pages = 1048576;
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break;
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case 5: /* 8GBit */
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dimm->nr_pages = 2097152;
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break;
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}
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dimm->grain = 8;
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dimm->dtype = cs_struct ? DEV_X16 : DEV_X8;
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dimm->mtype = (config & SDRAM_CONFIG_REGISTERED_MASK) ?
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MEM_RDDR3 : MEM_DDR3;
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dimm->edac_mode = EDAC_SECDED;
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}
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}
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static const struct of_device_id axp_mc_of_match[] = {
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{.compatible = "marvell,armada-xp-sdram-controller",},
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{},
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};
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MODULE_DEVICE_TABLE(of, axp_mc_of_match);
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static int axp_mc_probe(struct platform_device *pdev)
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{
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struct axp_mc_drvdata *drvdata;
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struct edac_mc_layer layers[1];
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const struct of_device_id *id;
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struct mem_ctl_info *mci;
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struct resource *r;
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void __iomem *base;
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uint32_t config;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "Unable to get mem resource\n");
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return -ENODEV;
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}
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base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(base)) {
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dev_err(&pdev->dev, "Unable to map regs\n");
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return PTR_ERR(base);
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}
|
||||
|
||||
config = readl(base + SDRAM_CONFIG_REG);
|
||||
if (!(config & SDRAM_CONFIG_ECC_MASK)) {
|
||||
dev_warn(&pdev->dev, "SDRAM ECC is not enabled");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
|
||||
layers[0].size = SDRAM_NUM_CS;
|
||||
layers[0].is_virt_csrow = true;
|
||||
|
||||
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata));
|
||||
if (!mci)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata = mci->pvt_info;
|
||||
drvdata->base = base;
|
||||
mci->pdev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, mci);
|
||||
|
||||
id = of_match_device(axp_mc_of_match, &pdev->dev);
|
||||
mci->edac_check = axp_mc_check;
|
||||
mci->mtype_cap = MEM_FLAG_DDR3;
|
||||
mci->edac_cap = EDAC_FLAG_SECDED;
|
||||
mci->mod_name = pdev->dev.driver->name;
|
||||
mci->ctl_name = id ? id->compatible : "unknown";
|
||||
mci->dev_name = dev_name(&pdev->dev);
|
||||
mci->scrub_mode = SCRUB_NONE;
|
||||
|
||||
axp_mc_read_config(mci);
|
||||
|
||||
/* These SoCs have a reduced width bus */
|
||||
if (of_machine_is_compatible("marvell,armada380") ||
|
||||
of_machine_is_compatible("marvell,armadaxp-98dx3236"))
|
||||
drvdata->width /= 2;
|
||||
|
||||
/* configure SBE threshold */
|
||||
/* it seems that SBEs are not captured otherwise */
|
||||
writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
|
||||
|
||||
/* clear cause registers */
|
||||
writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
|
||||
writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
|
||||
|
||||
/* clear counter registers */
|
||||
writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
|
||||
writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
|
||||
|
||||
if (edac_mc_add_mc(mci)) {
|
||||
edac_mc_free(mci);
|
||||
return -EINVAL;
|
||||
}
|
||||
edac_op_state = EDAC_OPSTATE_POLL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int axp_mc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
|
||||
|
||||
edac_mc_del_mc(&pdev->dev);
|
||||
edac_mc_free(mci);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver axp_mc_driver = {
|
||||
.probe = axp_mc_probe,
|
||||
.remove = axp_mc_remove,
|
||||
.driver = {
|
||||
.name = "armada_xp_mc_edac",
|
||||
.of_match_table = of_match_ptr(axp_mc_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
/************************ EDAC Device (L2 Cache) ***************************/
|
||||
|
||||
struct aurora_l2_drvdata {
|
||||
void __iomem *base;
|
||||
|
||||
char msg[128];
|
||||
|
||||
/* error injection via debugfs */
|
||||
uint32_t inject_addr;
|
||||
uint32_t inject_mask;
|
||||
uint8_t inject_ctl;
|
||||
|
||||
struct dentry *debugfs;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
static void aurora_l2_inject(struct aurora_l2_drvdata *drvdata)
|
||||
{
|
||||
drvdata->inject_addr &= AURORA_ERR_INJECT_CTL_ADDR_MASK;
|
||||
drvdata->inject_ctl &= AURORA_ERR_INJECT_CTL_EN_MASK;
|
||||
writel(0, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
|
||||
writel(drvdata->inject_mask, drvdata->base + AURORA_ERR_INJECT_MASK_REG);
|
||||
writel(drvdata->inject_addr | drvdata->inject_ctl, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void aurora_l2_check(struct edac_device_ctl_info *dci)
|
||||
{
|
||||
struct aurora_l2_drvdata *drvdata = dci->pvt_info;
|
||||
uint32_t cnt, src, txn, err, attr_cap, addr_cap, way_cap;
|
||||
unsigned int cnt_ce, cnt_ue;
|
||||
char *msg = drvdata->msg;
|
||||
size_t size = sizeof(drvdata->msg);
|
||||
size_t len = 0;
|
||||
|
||||
cnt = readl(drvdata->base + AURORA_ERR_CNT_REG);
|
||||
attr_cap = readl(drvdata->base + AURORA_ERR_ATTR_CAP_REG);
|
||||
addr_cap = readl(drvdata->base + AURORA_ERR_ADDR_CAP_REG);
|
||||
way_cap = readl(drvdata->base + AURORA_ERR_WAY_CAP_REG);
|
||||
|
||||
cnt_ce = (cnt & AURORA_ERR_CNT_CE_MASK) >> AURORA_ERR_CNT_CE_OFFSET;
|
||||
cnt_ue = (cnt & AURORA_ERR_CNT_UE_MASK) >> AURORA_ERR_CNT_UE_OFFSET;
|
||||
/* clear error counter registers */
|
||||
if (cnt_ce || cnt_ue)
|
||||
writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
|
||||
|
||||
if (!(attr_cap & AURORA_ERR_ATTR_CAP_VALID))
|
||||
goto clear_remaining;
|
||||
|
||||
src = (attr_cap & AURORA_ERR_ATTR_SRC_MSK) >> AURORA_ERR_ATTR_SRC_OFF;
|
||||
if (src <= 3)
|
||||
len += snprintf(msg+len, size-len, "src=CPU%d ", src);
|
||||
else
|
||||
len += snprintf(msg+len, size-len, "src=IO ");
|
||||
|
||||
txn = (attr_cap & AURORA_ERR_ATTR_TXN_MSK) >> AURORA_ERR_ATTR_TXN_OFF;
|
||||
switch (txn) {
|
||||
case 0:
|
||||
len += snprintf(msg+len, size-len, "txn=Data-Read ");
|
||||
break;
|
||||
case 1:
|
||||
len += snprintf(msg+len, size-len, "txn=Isn-Read ");
|
||||
break;
|
||||
case 2:
|
||||
len += snprintf(msg+len, size-len, "txn=Clean-Flush ");
|
||||
break;
|
||||
case 3:
|
||||
len += snprintf(msg+len, size-len, "txn=Eviction ");
|
||||
break;
|
||||
case 4:
|
||||
len += snprintf(msg+len, size-len,
|
||||
"txn=Read-Modify-Write ");
|
||||
break;
|
||||
}
|
||||
|
||||
err = (attr_cap & AURORA_ERR_ATTR_ERR_MSK) >> AURORA_ERR_ATTR_ERR_OFF;
|
||||
switch (err) {
|
||||
case 0:
|
||||
len += snprintf(msg+len, size-len, "err=CorrECC ");
|
||||
break;
|
||||
case 1:
|
||||
len += snprintf(msg+len, size-len, "err=UnCorrECC ");
|
||||
break;
|
||||
case 2:
|
||||
len += snprintf(msg+len, size-len, "err=TagParity ");
|
||||
break;
|
||||
}
|
||||
|
||||
len += snprintf(msg+len, size-len, "addr=0x%x ", addr_cap & AURORA_ERR_ADDR_CAP_ADDR_MASK);
|
||||
len += snprintf(msg+len, size-len, "index=0x%x ", (way_cap & AURORA_ERR_WAY_IDX_MSK) >> AURORA_ERR_WAY_IDX_OFF);
|
||||
len += snprintf(msg+len, size-len, "way=0x%x", (way_cap & AURORA_ERR_WAY_CAP_WAY_MASK) >> AURORA_ERR_WAY_CAP_WAY_OFFSET);
|
||||
|
||||
/* clear error capture registers */
|
||||
writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
|
||||
if (err) {
|
||||
/* UnCorrECC or TagParity */
|
||||
if (cnt_ue)
|
||||
cnt_ue--;
|
||||
edac_device_handle_ue(dci, 0, 0, drvdata->msg);
|
||||
} else {
|
||||
if (cnt_ce)
|
||||
cnt_ce--;
|
||||
edac_device_handle_ce(dci, 0, 0, drvdata->msg);
|
||||
}
|
||||
|
||||
clear_remaining:
|
||||
/* report remaining errors */
|
||||
while (cnt_ue--)
|
||||
edac_device_handle_ue(dci, 0, 0, "details unavailable (multiple errors)");
|
||||
while (cnt_ce--)
|
||||
edac_device_handle_ue(dci, 0, 0, "details unavailable (multiple errors)");
|
||||
}
|
||||
|
||||
static void aurora_l2_poll(struct edac_device_ctl_info *dci)
|
||||
{
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
struct aurora_l2_drvdata *drvdata = dci->pvt_info;
|
||||
#endif
|
||||
|
||||
aurora_l2_check(dci);
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
aurora_l2_inject(drvdata);
|
||||
#endif
|
||||
}
|
||||
|
||||
static const struct of_device_id aurora_l2_of_match[] = {
|
||||
{.compatible = "marvell,aurora-system-cache",},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, aurora_l2_of_match);
|
||||
|
||||
static int aurora_l2_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct aurora_l2_drvdata *drvdata;
|
||||
struct edac_device_ctl_info *dci;
|
||||
const struct of_device_id *id;
|
||||
uint32_t l2x0_aux_ctrl;
|
||||
void __iomem *base;
|
||||
struct resource *r;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!r) {
|
||||
dev_err(&pdev->dev, "Unable to get mem resource\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, r);
|
||||
if (IS_ERR(base)) {
|
||||
dev_err(&pdev->dev, "Unable to map regs\n");
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
l2x0_aux_ctrl = readl(base + L2X0_AUX_CTRL);
|
||||
if (!(l2x0_aux_ctrl & AURORA_ACR_PARITY_EN))
|
||||
dev_warn(&pdev->dev, "tag parity is not enabled");
|
||||
if (!(l2x0_aux_ctrl & AURORA_ACR_ECC_EN))
|
||||
dev_warn(&pdev->dev, "data ECC is not enabled");
|
||||
|
||||
dci = edac_device_alloc_ctl_info(sizeof(*drvdata),
|
||||
"cpu", 1, "L", 1, 2, NULL, 0, 0);
|
||||
if (!dci)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata = dci->pvt_info;
|
||||
drvdata->base = base;
|
||||
dci->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, dci);
|
||||
|
||||
id = of_match_device(aurora_l2_of_match, &pdev->dev);
|
||||
dci->edac_check = aurora_l2_poll;
|
||||
dci->mod_name = pdev->dev.driver->name;
|
||||
dci->ctl_name = id ? id->compatible : "unknown";
|
||||
dci->dev_name = dev_name(&pdev->dev);
|
||||
|
||||
/* clear registers */
|
||||
writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
|
||||
writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
|
||||
|
||||
if (edac_device_add_device(dci)) {
|
||||
edac_device_free_ctl_info(dci);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
drvdata->debugfs = edac_debugfs_create_dir(dev_name(&pdev->dev));
|
||||
if (drvdata->debugfs) {
|
||||
edac_debugfs_create_x32("inject_addr", 0644,
|
||||
drvdata->debugfs,
|
||||
&drvdata->inject_addr);
|
||||
edac_debugfs_create_x32("inject_mask", 0644,
|
||||
drvdata->debugfs,
|
||||
&drvdata->inject_mask);
|
||||
edac_debugfs_create_x8("inject_ctl", 0644,
|
||||
drvdata->debugfs, &drvdata->inject_ctl);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aurora_l2_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
struct aurora_l2_drvdata *drvdata = dci->pvt_info;
|
||||
|
||||
edac_debugfs_remove_recursive(drvdata->debugfs);
|
||||
#endif
|
||||
edac_device_del_device(&pdev->dev);
|
||||
edac_device_free_ctl_info(dci);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver aurora_l2_driver = {
|
||||
.probe = aurora_l2_probe,
|
||||
.remove = aurora_l2_remove,
|
||||
.driver = {
|
||||
.name = "aurora_l2_edac",
|
||||
.of_match_table = of_match_ptr(aurora_l2_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
/************************ Driver registration ******************************/
|
||||
|
||||
static struct platform_driver * const drivers[] = {
|
||||
&axp_mc_driver,
|
||||
&aurora_l2_driver,
|
||||
};
|
||||
|
||||
static int __init armada_xp_edac_init(void)
|
||||
{
|
||||
int res;
|
||||
|
||||
/* only polling is supported */
|
||||
edac_op_state = EDAC_OPSTATE_POLL;
|
||||
|
||||
res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
||||
if (res)
|
||||
pr_warn("Aramda XP EDAC drivers fail to register\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
module_init(armada_xp_edac_init);
|
||||
|
||||
static void __exit armada_xp_edac_exit(void)
|
||||
{
|
||||
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
||||
}
|
||||
module_exit(armada_xp_edac_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Pengutronix");
|
||||
MODULE_DESCRIPTION("EDAC Drivers for Marvell Armada XP SDRAM and L2 Cache Controller");
|
||||
|
|
@ -138,3 +138,14 @@ void edac_debugfs_create_x16(const char *name, umode_t mode,
|
|||
debugfs_create_x16(name, mode, parent, value);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(edac_debugfs_create_x16);
|
||||
|
||||
/* Wrapper for debugfs_create_x32() */
|
||||
void edac_debugfs_create_x32(const char *name, umode_t mode,
|
||||
struct dentry *parent, u32 *value)
|
||||
{
|
||||
if (!parent)
|
||||
parent = edac_debugfs;
|
||||
|
||||
debugfs_create_x32(name, mode, parent, value);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(edac_debugfs_create_x32);
|
||||
|
|
|
|||
|
|
@ -82,6 +82,8 @@ void edac_debugfs_create_x8(const char *name, umode_t mode,
|
|||
struct dentry *parent, u8 *value);
|
||||
void edac_debugfs_create_x16(const char *name, umode_t mode,
|
||||
struct dentry *parent, u16 *value);
|
||||
void edac_debugfs_create_x32(const char *name, umode_t mode,
|
||||
struct dentry *parent, u32 *value);
|
||||
#else
|
||||
static inline void edac_debugfs_init(void) { }
|
||||
static inline void edac_debugfs_exit(void) { }
|
||||
|
|
@ -96,6 +98,8 @@ static inline void edac_debugfs_create_x8(const char *name, umode_t mode,
|
|||
struct dentry *parent, u8 *value) { }
|
||||
static inline void edac_debugfs_create_x16(const char *name, umode_t mode,
|
||||
struct dentry *parent, u16 *value) { }
|
||||
static inline void edac_debugfs_create_x32(const char *name, umode_t mode,
|
||||
struct dentry *parent, u32 *value) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue