From 8818857f12f2de21f479e39d75c2f3a40b71f77e Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Wed, 22 Sep 2021 09:22:50 -0700 Subject: [PATCH] clk: qcom: clk-cpu-sdxlemur: Use lucid_5lpe ops with latch bypass The CPU PLLs latch interface is custom and not entirely reliable. So instead use the standard lucid_5lpe ops and bypass the latch interface. Change-Id: I0bc46e329ed5e135f26a08a4f09dd1872013ed7a Signed-off-by: Mike Tipton --- drivers/clk/qcom/clk-cpu-sdxlemur.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-cpu-sdxlemur.c b/drivers/clk/qcom/clk-cpu-sdxlemur.c index b2daf0519ccd..1ddc17fedf0a 100644 --- a/drivers/clk/qcom/clk-cpu-sdxlemur.c +++ b/drivers/clk/qcom/clk-cpu-sdxlemur.c @@ -299,6 +299,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { .vco_table = lucid_5lpe_vco, .num_vco = ARRAY_SIZE(lucid_5lpe_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE], + .flags = BYPASS_LATCH, .clkr = { .hw.init = &(struct clk_init_data){ .name = "apcs_cpu_pll", @@ -306,7 +307,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { .fw_name = "bi_tcxo_ao", }, .num_parents = 1, - .ops = &clk_alpha_pll_lucid_5lpe_sdx_cpu_ops, + .ops = &clk_alpha_pll_lucid_5lpe_ops, }, .vdd_data = { .vdd_class = &vdd_pll,