From 8873580db9f71c8cc2567e34bbd7affac53f9d32 Mon Sep 17 00:00:00 2001
From: Govindaraj Rajagopal <grajagop@qti.qualcomm.com>
Date: Thu, 16 Jul 2020 13:39:01 +0530
Subject: [PATCH] ARM: dts: msm: Remove core clock reset for shima

Remove core clock reset to be inline with lahaina sequence.

Change-Id: If6e9bde30ec4f73535bf53303805c43cb9b6f693
---
 qcom/shima-vidc.dtsi | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/qcom/shima-vidc.dtsi b/qcom/shima-vidc.dtsi
index 1d591307794e..c345c997e467 100644
--- a/qcom/shima-vidc.dtsi
+++ b/qcom/shima-vidc.dtsi
@@ -26,9 +26,8 @@
 		qcom,clock-configs = <0x0 0x0 0x1 0x1>;
 		qcom,allowed-clock-rates = <240000000 338000000
 			364800000>;
-		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
-			<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
-		reset-names = "video_axi_reset", "video_core_reset";
+		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+		reset-names = "video_axi_reset";
 
 		qcom,reg-presets = <0xB0088 0x0 0x11>;