mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
This is the bulk of pin control changes for the v4.3 development
cycle
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing
all call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a
combined call to irq_set_chained_handler_and_data(). This
series was created by Thomas Gleixner after the problem was
observed by Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which
is way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs
from IRQ numbers. The goal is to get rid of the irq number
from the handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw
spinlocks in IRQ handlers to play nice with the realtime
patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner
sun4i driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC
subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.
Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.
[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
This commit is contained in:
Linus Torvalds
commit
88a99886c2
78 changed files with 12274 additions and 954 deletions
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@ -48,7 +48,7 @@ Optional subnode-properties:
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Examples:
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pinctrl@01c20800 {
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun5i-a13-pinctrl";
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reg = <0x01c20800 0x400>;
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#address-cells = <1>;
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@ -68,3 +68,38 @@ pinctrl@01c20800 {
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allwinner,pull = <0>;
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};
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};
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GPIO and interrupt controller
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-----------------------------
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This hardware also acts as a GPIO controller and an interrupt
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controller.
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Consumers that would want to refer to one or the other (or both)
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should provide through the usual *-gpios and interrupts properties a
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cell with 3 arguments, first the number of the bank, then the pin
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inside that bank, and finally the flags for the GPIO/interrupts.
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Example:
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xio: gpio@38 {
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compatible = "nxp,pcf8574a";
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reg = <0x38>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&pio>;
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interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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reg_usb1_vbus: usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
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};
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@ -0,0 +1,86 @@
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Conexant Digicolor CX92755 General Purpose Pin Mapping
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This document describes the device tree binding of the pin mapping hardware
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modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
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Digicolor series of SoCs.
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=== Pin Controller Node ===
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Required Properties:
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- compatible: Must be "cnxt,cx92755-pinctrl"
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- reg: Base address of the General Purpose Pin Mapping register block and the
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size of the block.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Must be <2>. The first cell is the pin number and the
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second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
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for possible values.
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For example, the following is the bare minimum node:
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pinctrl: pinctrl@f0000e20 {
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compatible = "cnxt,cx92755-pinctrl";
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reg = <0xf0000e20 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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As a pin controller device, in addition to the required properties, this node
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should also contain the pin configuration nodes that client devices reference,
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if any.
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For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
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=== Pin Configuration Node ===
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Each pin configuration node is a sub-node of the pin controller node and is a
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container of an arbitrary number of subnodes, called pin group nodes in this
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document.
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Please refer to the pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the definition of a
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"pin configuration node".
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=== Pin Group Node ===
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A pin group node specifies the desired pin mux for an arbitrary number of
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pins. The name of the pin group node is optional and not used.
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A pin group node only affects the properties specified in the node, and has no
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effect on any properties that are omitted.
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The pin group node accepts a subset of the generic pin config properties. For
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details generic pin config properties, please refer to pinctrl-bindings.txt
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and <include/linux/pinctrl/pinconfig-generic.h>.
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Required Pin Group Node Properties:
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- pins: Multiple strings. Specifies the name(s) of one or more pins to be
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configured by this node. The format of a pin name string is "GP_xy", where x
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is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
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- function: String. Specifies the pin mux selection. Values must be one of:
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"gpio", "client_a", "client_b", "client_c"
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Example:
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pinctrl: pinctrl@f0000e20 {
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compatible = "cnxt,cx92755-pinctrl";
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reg = <0xf0000e20 0x100>;
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uart0_default: uart0_active {
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data_signals {
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pins = "GP_O0", "GP_O1";
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function = "client_b";
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};
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};
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};
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uart0: uart@f0000740 {
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compatible = "cnxt,cx92755-usart";
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...
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pinctrl-0 = <&uart0_default>;
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pinctrl-names = "default";
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};
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In the example above, a single pin group configuration node defines the
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"client select" for the Rx and Tx signals of uart0. The uart0 node references
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that pin configuration node using the &uart0_default phandle.
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@ -7,8 +7,13 @@ of PMIC's from Qualcomm.
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Usage: required
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Value type: <string>
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Definition: Should contain one of:
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"qcom,pm8018-mpp",
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"qcom,pm8038-mpp",
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"qcom,pm8821-mpp",
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"qcom,pm8841-mpp",
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"qcom,pm8916-mpp",
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"qcom,pm8917-mpp",
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"qcom,pm8921-mpp",
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"qcom,pm8941-mpp",
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"qcom,pma8084-mpp",
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@ -77,12 +82,9 @@ to specify in a pin configuration subnode:
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Valid values are:
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"normal",
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"paired",
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"dtest1",
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"dtest2",
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"dtest3",
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"dtest4"
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"digital",
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"analog",
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"sink"
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- bias-disable:
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Usage: optional
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@ -127,12 +129,18 @@ to specify in a pin configuration subnode:
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Definition: Selects the power source for the specified pins. Valid power
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sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
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- qcom,analog-mode:
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- qcom,analog-level:
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Usage: optional
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Value type: <none>
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Definition: Selects Analog mode of operation: combined with input-enable
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and/or output-high, output-low MPP could operate as
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Bidirectional Logic, Analog Input, Analog Output.
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Value type: <u32>
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Definition: Selects the source for analog output. Valued values are
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defined in <dt-binding/pinctrl/qcom,pmic-mpp.h>
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PMIC_MPP_AOUT_LVL_*
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- qcom,dtest:
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Usage: optional
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Value type: <u32>
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Definition: Selects which dtest rail to be routed in the various functions.
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Valid values are 1-4
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- qcom,amux-route:
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Usage: optional
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@ -140,6 +148,10 @@ to specify in a pin configuration subnode:
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Definition: Selects the source for analog input. Valid values are
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defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
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PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6...
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- qcom,paired:
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Usage: optional
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Value type: <none>
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Definition: Indicates that the pin should be operating in paired mode.
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Example:
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@ -156,7 +168,7 @@ Example:
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pm8841_default: default {
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gpio {
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pins = "mpp1", "mpp2", "mpp3", "mpp4";
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function = "normal";
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function = "digital";
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input-enable;
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power-source = <PM8841_MPP_S3>;
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};
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@ -58,12 +58,12 @@ are parsed through phandles and processed purely based on their content.
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Pin Configuration Node Properties:
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- renesas,pins : An array of strings, each string containing the name of a pin.
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- renesas,groups : An array of strings, each string containing the name of a pin
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- pins : An array of strings, each string containing the name of a pin.
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- groups : An array of strings, each string containing the name of a pin
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group.
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- renesas,function: A string containing the name of the function to mux to the
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pin group(s) specified by the renesas,groups property
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- function: A string containing the name of the function to mux to the pin
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group(s) specified by the groups property.
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Valid values for pin, group and function names can be found in the group and
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function arrays of the PFC data file corresponding to the SoC
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@ -71,7 +71,9 @@ Pin Configuration Node Properties:
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The pin configuration parameters use the generic pinconf bindings defined in
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pinctrl-bindings.txt in this directory. The supported parameters are
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bias-disable, bias-pull-up and bias-pull-down.
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bias-disable, bias-pull-up, bias-pull-down and power-source. For pins that
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have a configurable I/O voltage, the power-source value should be the
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nominal I/O voltage in millivolts.
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GPIO
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@ -141,19 +143,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
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mmcif_pins: mmcif {
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mux {
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renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
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renesas,function = "mmc0";
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groups = "mmc0_data8_0", "mmc0_ctrl_0";
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function = "mmc0";
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};
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cfg {
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renesas,groups = "mmc0_data8_0";
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renesas,pins = "PORT279";
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groups = "mmc0_data8_0";
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pins = "PORT279";
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bias-pull-up;
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};
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};
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scifa4_pins: scifa4 {
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renesas,groups = "scifa4_data", "scifa4_ctrl";
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renesas,function = "scifa4";
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groups = "scifa4_data", "scifa4_ctrl";
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function = "scifa4";
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};
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};
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@ -3,7 +3,9 @@ ST Ericsson Nomadik pinmux controller
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Required properties:
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- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
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"stericsson,stn8815-pinctrl"
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- reg: Should contain the register physical address and length of the PRCMU.
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- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
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(these have the register ranges used by the pin controller).
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- prcm: phandle to the PRCMU managing the back end of this pin controller
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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@ -74,7 +76,8 @@ Example board file extract:
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pinctrl@80157000 {
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compatible = "stericsson,db8500-pinctrl";
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reg = <0x80157000 0x2000>;
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nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
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prcm = <&prcmu>;
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pinctrl-names = "default";
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Loading…
Reference in a new issue