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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 00:24:41 -04:00
Merge "ARM: dts: msm: Add glink entries for Holi"
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qctecmdr
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262
qcom/holi.dtsi
262
qcom/holi.dtsi
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@ -3,6 +3,7 @@
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#include <dt-bindings/clock/qcom,gpucc-holi.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Holi";
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@ -533,6 +534,267 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsr_mutex_block: syscon@340000 {
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compatible = "syscon";
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reg = <0x340000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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qcom,smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
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qcom,entry-name = "ipa";
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#qcom,smem-state-cells = <1>;
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};
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/* ipa - inbound entry from mss */
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smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
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qcom,entry-name = "ipa";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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cdsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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cdsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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rpm_msg_ram: memory@045f0000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x45f0000 0x7000>;
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "rpm_smem";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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qcom,rpm_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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qcom,notify-edges = <&glink_modem>,
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<&glink_adsp>,
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<&glink_cdsp>;
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};
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};
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qcom,glink {
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compatible = "qcom,glink";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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glink_modem: modem {
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qcom,remote-pid = <1>;
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transport = "smem";
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mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "mpss_smem";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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label = "modem";
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qcom,glink-label = "mpss";
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qcom,modem_qrtr {
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qcom,glink-channels = "IPCRTR";
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qcom,low-latency;
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qcom,intents = <0x800 5
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0x2000 3
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0x4400 2>;
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};
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qcom,modem_ds {
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qcom,glink-channels = "DS";
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qcom,intents = <0x4000 0x2>;
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};
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qcom,modem_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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qcom,notify-edges = <&glink_adsp>;
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};
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};
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glink_adsp: adsp {
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qcom,remote-pid = <2>;
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transport = "smem";
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mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "adsp_smem";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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label = "adsp";
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qcom,glink-label = "lpass";
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qcom,adsp_qrtr {
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qcom,glink-channels = "IPCRTR";
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qcom,intents = <0x800 5
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0x2000 3
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0x4400 2>;
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};
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qcom,adsp_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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qcom,notify-edges = <&glink_modem>;
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};
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qcom,pmic_glink_rpmsg {
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qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
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};
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qcom,pmic_glink_log_rpmsg {
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qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
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qcom,intents = <0x800 5
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0xc00 3>;
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};
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};
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glink_cdsp: cdsp {
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qcom,remote-pid = <5>;
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transport = "smem";
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mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "dsps_smem";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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label = "cdsp";
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qcom,glink-label = "cdsp";
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qcom,cdsp_qrtr {
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qcom,glink-channels = "IPCRTR";
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qcom,intents = <0x800 5
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0x2000 3
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0x4400 2>;
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};
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};
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};
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qcom,glinkpkt {
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compatible = "qcom,glinkpkt";
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qcom,glinkpkt-at-mdm0 {
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qcom,glinkpkt-edge = "mpss";
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qcom,glinkpkt-ch-name = "DS";
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qcom,glinkpkt-dev-name = "at_mdm0";
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};
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qcom,glinkpkt-apr-apps2 {
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qcom,glinkpkt-edge = "adsp";
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qcom,glinkpkt-ch-name = "apr_apps2";
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qcom,glinkpkt-dev-name = "apr_apps2";
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};
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qcom,glinkpkt-data40-cntl {
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qcom,glinkpkt-edge = "mpss";
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qcom,glinkpkt-ch-name = "DATA40_CNTL";
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qcom,glinkpkt-dev-name = "smdcntl8";
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};
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qcom,glinkpkt-data1 {
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qcom,glinkpkt-edge = "mpss";
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qcom,glinkpkt-ch-name = "DATA1";
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qcom,glinkpkt-dev-name = "smd7";
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};
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qcom,glinkpkt-data4 {
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qcom,glinkpkt-edge = "mpss";
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qcom,glinkpkt-ch-name = "DATA4";
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qcom,glinkpkt-dev-name = "smd8";
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};
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qcom,glinkpkt-data11 {
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qcom,glinkpkt-edge = "mpss";
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qcom,glinkpkt-ch-name = "DATA11";
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qcom,glinkpkt-dev-name = "smd11";
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};
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};
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};
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#include "holi-pinctrl.dtsi"
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