From c1413270ce4d507cd03b4f93415e4d3019677fe0 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Tue, 6 Apr 2021 16:31:43 +0530 Subject: [PATCH] Revert "ARM: dts: msm: Use PCIe_MSI for Shima" This reverts commit 6b84a80dde1ab6801f606e9f81cea291ef462da7. Commit 6b84a80dde1ab6 ("ARM: dts: msm: Use PCIe_MSI for Shima") revert the synopsys MSI controller to GIC interrupt controller. We are facing an issue where wake MSI is enabled after DRV suspend by the time PCIe clocks are off and also there is an interrupt latency with SNPS controller. Change-Id: Iaf47c2c8b9c188183d6ad0e72bb7d05b0b7262b7 --- qcom/shima-pcie.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 679206758308..4f9b6aef51ab 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi_snps>; + msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -204,15 +204,6 @@ }; }; - pcie0_msi_snps: qcom,pcie0_msi@a0000000 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0xa0000000 0x0>; - interrupt-parent = <&intc>; - interrupts = ; - qcom,snps; - }; - pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller;