mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
[MIPS] TXx9: Reorganize PCI code
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
22b1d707ff
commit
89d63fe179
27 changed files with 1851 additions and 2011 deletions
23
include/asm-mips/txx9/generic.h
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23
include/asm-mips/txx9/generic.h
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@ -0,0 +1,23 @@
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/*
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* linux/include/asm-mips/txx9/generic.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_TXX9_GENERIC_H
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#define __ASM_TXX9_GENERIC_H
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#include <linux/init.h>
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#include <linux/ioport.h> /* for struct resource */
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extern struct resource txx9_ce_res[];
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extern char txx9_pcode_str[8];
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void txx9_reg_res_init(unsigned int pcode, unsigned long base,
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unsigned long size);
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extern unsigned int txx9_master_clock;
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extern unsigned int txx9_cpu_clock;
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extern unsigned int txx9_gbus_clock;
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#endif /* __ASM_TXX9_GENERIC_H */
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36
include/asm-mips/txx9/pci.h
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36
include/asm-mips/txx9/pci.h
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@ -0,0 +1,36 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_TXX9_PCI_H
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#define __ASM_TXX9_PCI_H
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#include <linux/pci.h>
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extern struct pci_controller txx9_primary_pcic;
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struct pci_controller *
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txx9_alloc_pci_controller(struct pci_controller *pcic,
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unsigned long mem_base, unsigned long mem_size,
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unsigned long io_base, unsigned long io_size);
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int txx9_pci66_check(struct pci_controller *hose, int top_bus,
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int current_bus);
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extern int txx9_pci_mem_high __initdata;
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extern int txx9_pci_option;
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#define TXX9_PCI_OPT_PICMG 0x0002
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#define TXX9_PCI_OPT_CLK_33 0x0008
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#define TXX9_PCI_OPT_CLK_66 0x0010
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#define TXX9_PCI_OPT_CLK_MASK \
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(TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
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#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
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enum txx9_pci_err_action {
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TXX9_PCI_ERR_REPORT,
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TXX9_PCI_ERR_IGNORE,
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TXX9_PCI_ERR_PANIC,
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};
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extern enum txx9_pci_err_action txx9_pci_err_action;
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#endif /* __ASM_TXX9_PCI_H */
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@ -29,10 +29,33 @@
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#include <asm/txx9/tx4927.h>
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#define RBTX4927_PCIMEM 0x08000000
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#define RBTX4927_PCIMEM_SIZE 0x08000000
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#define RBTX4927_PCIIO 0x16000000
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#define RBTX4927_PCIIO_SIZE 0x01000000
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#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL)
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/* bits for ISTAT/IMASK/IMSTAT */
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#define RBTX4927_INTB_PCID 0
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#define RBTX4927_INTB_PCIC 1
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#define RBTX4927_INTB_PCIB 2
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#define RBTX4927_INTB_PCIA 3
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#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
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#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
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#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
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#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
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#define RBTX4927_IRQ_IOC (TX4927_IRQ_PIC_BEG + TX4927_NUM_IR)
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#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
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#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
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#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
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#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
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#ifdef CONFIG_PCI
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#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
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#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
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#else
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#define TBTX4927_ISA_IO_OFFSET 0
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#define RBTX4927_ISA_IO_OFFSET 0
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#endif
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#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
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@ -41,7 +64,7 @@
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#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
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#define RBTX4927_SW_RESET_ENABLE_SET 0x01
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#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
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#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
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#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
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int toshiba_rbtx4927_irq_nested(int sw_irq);
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@ -316,4 +316,8 @@ struct tx3927_ccfg_reg {
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#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
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#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
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struct pci_controller;
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void __init tx3927_pcic_setup(struct pci_controller *channel,
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unsigned long sdram_size, int extarb);
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#endif /* __ASM_TXX9_TX3927_H */
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@ -27,7 +27,10 @@
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#ifndef __ASM_TXX9_TX4927_H
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#define __ASM_TXX9_TX4927_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9/tx4927pcic.h>
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#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
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#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
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@ -43,15 +46,6 @@
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#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
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#define TX4927_CCFG_TOE 0x00004000
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#define TX4927_CCFG_WR 0x00008000
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#define TX4927_CCFG_TINTDIS 0x01000000
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#define TX4927_PCIMEM 0x08000000
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#define TX4927_PCIMEM_SIZE 0x08000000
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#define TX4927_PCIIO 0x16000000
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#define TX4927_PCIIO_SIZE 0x01000000
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#define TX4927_SDRAMC_REG 0xff1f8000
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#define TX4927_EBUSC_REG 0xff1f9000
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#define TX4927_PCIC_REG 0xff1fd000
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#define TX4927_NR_TMR 3
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#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
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/* bits for ISTAT3/IMASK3/IMSTAT3 */
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#define TX4927_INT3B_PCID 0
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#define TX4927_INT3B_PCIC 1
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#define TX4927_INT3B_PCIB 2
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#define TX4927_INT3B_PCIA 3
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#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
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#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
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#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
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#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
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#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
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#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
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#define TX4927_IR_PCIC 16
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#define TX4927_IR_PCIERR 22
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#define TX4927_IR_PCIPMA 23
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#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
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#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
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#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
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#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
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#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
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#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
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#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
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#ifdef _LANGUAGE_ASSEMBLY
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#define _CONST64(c) c
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#else
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#define _CONST64(c) c##ull
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#include <asm/byteorder.h>
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#define TX4927_NUM_IR 32
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struct tx4927_sdramc_reg {
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volatile unsigned long long cr[4];
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@ -104,177 +71,158 @@ struct tx4927_ebusc_reg {
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};
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struct tx4927_ccfg_reg {
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volatile unsigned long long ccfg;
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volatile unsigned long long crir;
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volatile unsigned long long pcfg;
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volatile unsigned long long tear;
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volatile unsigned long long clkctr;
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volatile unsigned long long unused0;
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volatile unsigned long long garbc;
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volatile unsigned long long unused1;
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volatile unsigned long long unused2;
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volatile unsigned long long ramp;
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u64 ccfg;
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u64 crir;
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u64 pcfg;
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u64 toea;
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u64 clkctr;
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u64 unused0;
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u64 garbc;
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u64 unused1;
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u64 unused2;
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u64 ramp;
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};
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struct tx4927_pcic_reg {
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volatile unsigned long pciid;
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volatile unsigned long pcistatus;
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volatile unsigned long pciccrev;
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volatile unsigned long pcicfg1;
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volatile unsigned long p2gm0plbase; /* +10 */
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volatile unsigned long p2gm0pubase;
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volatile unsigned long p2gm1plbase;
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volatile unsigned long p2gm1pubase;
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volatile unsigned long p2gm2pbase; /* +20 */
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volatile unsigned long p2giopbase;
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volatile unsigned long unused0;
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volatile unsigned long pcisid;
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volatile unsigned long unused1; /* +30 */
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volatile unsigned long pcicapptr;
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volatile unsigned long unused2;
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volatile unsigned long pcicfg2;
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volatile unsigned long g2ptocnt; /* +40 */
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volatile unsigned long unused3[15];
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volatile unsigned long g2pstatus; /* +80 */
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volatile unsigned long g2pmask;
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volatile unsigned long pcisstatus;
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volatile unsigned long pcimask;
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volatile unsigned long p2gcfg; /* +90 */
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volatile unsigned long p2gstatus;
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volatile unsigned long p2gmask;
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volatile unsigned long p2gccmd;
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volatile unsigned long unused4[24]; /* +a0 */
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volatile unsigned long pbareqport; /* +100 */
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volatile unsigned long pbacfg;
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volatile unsigned long pbastatus;
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volatile unsigned long pbamask;
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volatile unsigned long pbabm; /* +110 */
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volatile unsigned long pbacreq;
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volatile unsigned long pbacgnt;
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volatile unsigned long pbacstate;
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volatile unsigned long long g2pmgbase[3]; /* +120 */
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volatile unsigned long long g2piogbase;
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volatile unsigned long g2pmmask[3]; /* +140 */
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volatile unsigned long g2piomask;
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volatile unsigned long long g2pmpbase[3]; /* +150 */
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volatile unsigned long long g2piopbase;
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volatile unsigned long pciccfg; /* +170 */
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volatile unsigned long pcicstatus;
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volatile unsigned long pcicmask;
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volatile unsigned long unused5;
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volatile unsigned long long p2gmgbase[3]; /* +180 */
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volatile unsigned long long p2giogbase;
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volatile unsigned long g2pcfgadrs; /* +1a0 */
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volatile unsigned long g2pcfgdata;
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volatile unsigned long unused6[8];
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volatile unsigned long g2pintack;
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volatile unsigned long g2pspc;
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volatile unsigned long unused7[12]; /* +1d0 */
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volatile unsigned long long pdmca; /* +200 */
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volatile unsigned long long pdmga;
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volatile unsigned long long pdmpa;
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volatile unsigned long long pdmcut;
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volatile unsigned long long pdmcnt; /* +220 */
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volatile unsigned long long pdmsts;
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volatile unsigned long long unused8[2];
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volatile unsigned long long pdmdb[4]; /* +240 */
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volatile unsigned long long pdmtdh; /* +260 */
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volatile unsigned long long pdmdms;
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};
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#endif /* _LANGUAGE_ASSEMBLY */
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/*
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* PCIC
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*/
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/* bits for G2PSTATUS/G2PMASK */
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#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
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#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
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#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
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/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
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#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
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/* bits for PBACFG */
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#define TX4927_PCIC_PBACFG_RPBA 0x00000004
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#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
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#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
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/* bits for G2PMnGBASE */
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#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
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/* bits for G2PIOGBASE */
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#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
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/* bits for PCICSTATUS/PCICMASK */
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#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
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/* bits for PCICCFG */
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#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
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#define TX4927_PCIC_PCICCFG_HRST 0x00000800
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#define TX4927_PCIC_PCICCFG_SRST 0x00000400
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#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
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#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
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#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
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#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
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#define TX4927_PCIC_PCICCFG_IISE 0x00000020
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#define TX4927_PCIC_PCICCFG_ATR 0x00000010
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#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
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/* bits for P2GMnGBASE */
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#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
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#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
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/* bits for P2GIOGBASE */
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#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
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#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
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#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
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#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
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/*
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* CCFG
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*/
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/* CCFG : Chip Configuration */
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#define TX4927_CCFG_WDRST 0x0000020000000000ULL
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#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
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#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
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#define TX4927_CCFG_TINTDIS 0x01000000
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#define TX4927_CCFG_PCI66 0x00800000
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#define TX4927_CCFG_PCIMIDE 0x00400000
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#define TX4927_CCFG_PCIXARB 0x00002000
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#define TX4927_CCFG_PCIMODE 0x00400000
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#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
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#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
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#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
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#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
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#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
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#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
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#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
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#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
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#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
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#define TX4927_CCFG_BEOW 0x00010000
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#define TX4927_CCFG_WR 0x00008000
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#define TX4927_CCFG_TOE 0x00004000
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#define TX4927_CCFG_PCIARB 0x00002000
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#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
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#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
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#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
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#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
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#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
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#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
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#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
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#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
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#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
|
||||
#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
|
||||
#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
|
||||
#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
|
||||
#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
|
||||
#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
|
||||
#define TX4927_CCFG_SYSSP_MASK 0x000000c0
|
||||
#define TX4927_CCFG_ENDIAN 0x00000004
|
||||
#define TX4927_CCFG_HALT 0x00000002
|
||||
#define TX4927_CCFG_ACEHOLD 0x00000001
|
||||
#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
|
||||
|
||||
/* PCFG : Pin Configuration */
|
||||
#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
|
||||
#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
|
||||
#define TX4927_PCFG_SYSCLKEN 0x08000000
|
||||
#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
|
||||
#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
|
||||
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
|
||||
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
|
||||
#define TX4927_PCFG_SEL2 0x00000200
|
||||
#define TX4927_PCFG_SEL1 0x00000100
|
||||
#define TX4927_PCFG_DMASEL_ALL 0x000000ff
|
||||
#define TX4927_PCFG_DMASEL0_MASK 0x00000003
|
||||
#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
|
||||
#define TX4927_PCFG_DMASEL2_MASK 0x00000030
|
||||
#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
|
||||
#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
|
||||
#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
|
||||
#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
|
||||
#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
|
||||
#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
|
||||
#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
|
||||
#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
|
||||
#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
|
||||
#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
|
||||
#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
|
||||
#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
|
||||
#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
|
||||
#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
|
||||
#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
|
||||
#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
|
||||
#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
|
||||
#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
|
||||
|
||||
/* CLKCTR : Clock Control */
|
||||
#define TX4927_CLKCTR_ACLCKD 0x02000000
|
||||
#define TX4927_CLKCTR_PIOCKD 0x01000000
|
||||
#define TX4927_CLKCTR_DMACKD 0x00800000
|
||||
#define TX4927_CLKCTR_PCICKD 0x00400000
|
||||
#define TX4927_CLKCTR_TM0CKD 0x00100000
|
||||
#define TX4927_CLKCTR_TM1CKD 0x00080000
|
||||
#define TX4927_CLKCTR_TM2CKD 0x00040000
|
||||
#define TX4927_CLKCTR_SIO0CKD 0x00020000
|
||||
#define TX4927_CLKCTR_SIO1CKD 0x00010000
|
||||
#define TX4927_CLKCTR_ACLRST 0x00000200
|
||||
#define TX4927_CLKCTR_PIORST 0x00000100
|
||||
#define TX4927_CLKCTR_DMARST 0x00000080
|
||||
#define TX4927_CLKCTR_PCIRST 0x00000040
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
#define TX4927_CLKCTR_TM0RST 0x00000010
|
||||
#define TX4927_CLKCTR_TM1RST 0x00000008
|
||||
#define TX4927_CLKCTR_TM2RST 0x00000004
|
||||
#define TX4927_CLKCTR_SIO0RST 0x00000002
|
||||
#define TX4927_CLKCTR_SIO1RST 0x00000001
|
||||
|
||||
#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
|
||||
#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
|
||||
#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
|
||||
#define tx4927_pcicptr \
|
||||
((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
|
||||
#define tx4927_ccfgptr \
|
||||
((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
|
||||
#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
/* utilities */
|
||||
static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
|
||||
{
|
||||
#ifdef CONFIG_32BIT
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
#endif
|
||||
____raw_writeq(____raw_readq(adr) & ~bits, adr);
|
||||
#ifdef CONFIG_32BIT
|
||||
local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
|
||||
{
|
||||
#ifdef CONFIG_32BIT
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
#endif
|
||||
____raw_writeq(____raw_readq(adr) | bits, adr);
|
||||
#ifdef CONFIG_32BIT
|
||||
local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* These functions are not interrupt safe. */
|
||||
static inline void tx4927_ccfg_clear(__u64 bits)
|
||||
{
|
||||
____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
|
||||
& ~(TX4927_CCFG_W1CBITS | bits),
|
||||
&tx4927_ccfgptr->ccfg);
|
||||
}
|
||||
static inline void tx4927_ccfg_set(__u64 bits)
|
||||
{
|
||||
____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
|
||||
& ~TX4927_CCFG_W1CBITS) | bits,
|
||||
&tx4927_ccfgptr->ccfg);
|
||||
}
|
||||
static inline void tx4927_ccfg_change(__u64 change, __u64 new)
|
||||
{
|
||||
____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
|
||||
& ~(TX4927_CCFG_W1CBITS | change)) |
|
||||
new,
|
||||
&tx4927_ccfgptr->ccfg);
|
||||
}
|
||||
|
||||
int tx4927_report_pciclk(void);
|
||||
int tx4927_pciclk66_setup(void);
|
||||
|
||||
#endif /* __ASM_TXX9_TX4927_H */
|
||||
|
|
|
|||
199
include/asm-mips/txx9/tx4927pcic.h
Normal file
199
include/asm-mips/txx9/tx4927pcic.h
Normal file
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* include/asm-mips/txx9/tx4927pcic.h
|
||||
* TX4927 PCI controller definitions.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_TX4927PCIC_H
|
||||
#define __ASM_TXX9_TX4927PCIC_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
struct tx4927_pcic_reg {
|
||||
u32 pciid;
|
||||
u32 pcistatus;
|
||||
u32 pciccrev;
|
||||
u32 pcicfg1;
|
||||
u32 p2gm0plbase; /* +10 */
|
||||
u32 p2gm0pubase;
|
||||
u32 p2gm1plbase;
|
||||
u32 p2gm1pubase;
|
||||
u32 p2gm2pbase; /* +20 */
|
||||
u32 p2giopbase;
|
||||
u32 unused0;
|
||||
u32 pcisid;
|
||||
u32 unused1; /* +30 */
|
||||
u32 pcicapptr;
|
||||
u32 unused2;
|
||||
u32 pcicfg2;
|
||||
u32 g2ptocnt; /* +40 */
|
||||
u32 unused3[15];
|
||||
u32 g2pstatus; /* +80 */
|
||||
u32 g2pmask;
|
||||
u32 pcisstatus;
|
||||
u32 pcimask;
|
||||
u32 p2gcfg; /* +90 */
|
||||
u32 p2gstatus;
|
||||
u32 p2gmask;
|
||||
u32 p2gccmd;
|
||||
u32 unused4[24]; /* +a0 */
|
||||
u32 pbareqport; /* +100 */
|
||||
u32 pbacfg;
|
||||
u32 pbastatus;
|
||||
u32 pbamask;
|
||||
u32 pbabm; /* +110 */
|
||||
u32 pbacreq;
|
||||
u32 pbacgnt;
|
||||
u32 pbacstate;
|
||||
u64 g2pmgbase[3]; /* +120 */
|
||||
u64 g2piogbase;
|
||||
u32 g2pmmask[3]; /* +140 */
|
||||
u32 g2piomask;
|
||||
u64 g2pmpbase[3]; /* +150 */
|
||||
u64 g2piopbase;
|
||||
u32 pciccfg; /* +170 */
|
||||
u32 pcicstatus;
|
||||
u32 pcicmask;
|
||||
u32 unused5;
|
||||
u64 p2gmgbase[3]; /* +180 */
|
||||
u64 p2giogbase;
|
||||
u32 g2pcfgadrs; /* +1a0 */
|
||||
u32 g2pcfgdata;
|
||||
u32 unused6[8];
|
||||
u32 g2pintack;
|
||||
u32 g2pspc;
|
||||
u32 unused7[12]; /* +1d0 */
|
||||
u64 pdmca; /* +200 */
|
||||
u64 pdmga;
|
||||
u64 pdmpa;
|
||||
u64 pdmctr;
|
||||
u64 pdmcfg; /* +220 */
|
||||
u64 pdmsts;
|
||||
};
|
||||
|
||||
/* bits for PCICMD */
|
||||
/* see PCI_COMMAND_XXX in linux/pci_regs.h */
|
||||
|
||||
/* bits for PCISTAT */
|
||||
/* see PCI_STATUS_XXX in linux/pci_regs.h */
|
||||
|
||||
/* bits for IOBA/MBA */
|
||||
/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
|
||||
|
||||
/* bits for G2PSTATUS/G2PMASK */
|
||||
#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
|
||||
#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
|
||||
#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
|
||||
|
||||
/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
|
||||
#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
|
||||
|
||||
/* bits for PBACFG */
|
||||
#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
|
||||
#define TX4927_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
|
||||
#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
|
||||
|
||||
/* bits for PBASTATUS/PBAMASK */
|
||||
#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
|
||||
#define TX4927_PCIC_PBASTATUS_BM 0x00000001
|
||||
|
||||
/* bits for G2PMnGBASE */
|
||||
#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
|
||||
|
||||
/* bits for G2PIOGBASE */
|
||||
#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
|
||||
|
||||
/* bits for PCICSTATUS/PCICMASK */
|
||||
#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
|
||||
#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
|
||||
#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
|
||||
#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
|
||||
#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
|
||||
#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
|
||||
#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
|
||||
#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
|
||||
#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
|
||||
#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
|
||||
|
||||
/* bits for PCICCFG */
|
||||
#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
|
||||
#define TX4927_PCIC_PCICCFG_HRST 0x00000800
|
||||
#define TX4927_PCIC_PCICCFG_SRST 0x00000400
|
||||
#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
|
||||
#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
|
||||
#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
|
||||
#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
|
||||
#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
|
||||
#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
|
||||
#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
|
||||
#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
|
||||
|
||||
/* bits for P2GMnGBASE */
|
||||
#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
|
||||
#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
|
||||
|
||||
/* bits for P2GIOGBASE */
|
||||
#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
|
||||
#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
|
||||
|
||||
#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
|
||||
#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
|
||||
|
||||
/* bits for PDMCFG */
|
||||
#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
|
||||
#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
|
||||
#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
|
||||
#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
|
||||
#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
|
||||
#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
|
||||
#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
|
||||
#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
|
||||
#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
|
||||
|
||||
/* bits for PDMSTS */
|
||||
#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
|
||||
#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
|
||||
#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
|
||||
#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
|
||||
#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
|
||||
#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
|
||||
#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
|
||||
#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
|
||||
#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
|
||||
#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
|
||||
#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
|
||||
#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
|
||||
#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
|
||||
#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
|
||||
#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
|
||||
|
||||
struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
|
||||
struct pci_controller *channel);
|
||||
void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
|
||||
struct pci_controller *channel, int extarb);
|
||||
void tx4927_report_pcic_status(void);
|
||||
|
||||
#endif /* __ASM_TXX9_TX4927PCIC_H */
|
||||
|
|
@ -12,6 +12,9 @@
|
|||
#ifndef __ASM_TXX9_TX4938_H
|
||||
#define __ASM_TXX9_TX4938_H
|
||||
|
||||
/* some controllers are compatible with 4927 */
|
||||
#include <asm/txx9/tx4927.h>
|
||||
|
||||
#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
|
||||
#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
|
||||
|
||||
|
|
@ -51,9 +54,6 @@
|
|||
#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
|
||||
#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _CONST64(c) c
|
||||
#else
|
||||
#define _CONST64(c) c##ull
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
|
@ -113,68 +113,6 @@ struct tx4938_dma_reg {
|
|||
endian_def_l2(unused0, mcr);
|
||||
};
|
||||
|
||||
struct tx4938_pcic_reg {
|
||||
volatile unsigned long pciid;
|
||||
volatile unsigned long pcistatus;
|
||||
volatile unsigned long pciccrev;
|
||||
volatile unsigned long pcicfg1;
|
||||
volatile unsigned long p2gm0plbase; /* +10 */
|
||||
volatile unsigned long p2gm0pubase;
|
||||
volatile unsigned long p2gm1plbase;
|
||||
volatile unsigned long p2gm1pubase;
|
||||
volatile unsigned long p2gm2pbase; /* +20 */
|
||||
volatile unsigned long p2giopbase;
|
||||
volatile unsigned long unused0;
|
||||
volatile unsigned long pcisid;
|
||||
volatile unsigned long unused1; /* +30 */
|
||||
volatile unsigned long pcicapptr;
|
||||
volatile unsigned long unused2;
|
||||
volatile unsigned long pcicfg2;
|
||||
volatile unsigned long g2ptocnt; /* +40 */
|
||||
volatile unsigned long unused3[15];
|
||||
volatile unsigned long g2pstatus; /* +80 */
|
||||
volatile unsigned long g2pmask;
|
||||
volatile unsigned long pcisstatus;
|
||||
volatile unsigned long pcimask;
|
||||
volatile unsigned long p2gcfg; /* +90 */
|
||||
volatile unsigned long p2gstatus;
|
||||
volatile unsigned long p2gmask;
|
||||
volatile unsigned long p2gccmd;
|
||||
volatile unsigned long unused4[24]; /* +a0 */
|
||||
volatile unsigned long pbareqport; /* +100 */
|
||||
volatile unsigned long pbacfg;
|
||||
volatile unsigned long pbastatus;
|
||||
volatile unsigned long pbamask;
|
||||
volatile unsigned long pbabm; /* +110 */
|
||||
volatile unsigned long pbacreq;
|
||||
volatile unsigned long pbacgnt;
|
||||
volatile unsigned long pbacstate;
|
||||
volatile unsigned long long g2pmgbase[3]; /* +120 */
|
||||
volatile unsigned long long g2piogbase;
|
||||
volatile unsigned long g2pmmask[3]; /* +140 */
|
||||
volatile unsigned long g2piomask;
|
||||
volatile unsigned long long g2pmpbase[3]; /* +150 */
|
||||
volatile unsigned long long g2piopbase;
|
||||
volatile unsigned long pciccfg; /* +170 */
|
||||
volatile unsigned long pcicstatus;
|
||||
volatile unsigned long pcicmask;
|
||||
volatile unsigned long unused5;
|
||||
volatile unsigned long long p2gmgbase[3]; /* +180 */
|
||||
volatile unsigned long long p2giogbase;
|
||||
volatile unsigned long g2pcfgadrs; /* +1a0 */
|
||||
volatile unsigned long g2pcfgdata;
|
||||
volatile unsigned long unused6[8];
|
||||
volatile unsigned long g2pintack;
|
||||
volatile unsigned long g2pspc;
|
||||
volatile unsigned long unused7[12]; /* +1d0 */
|
||||
volatile unsigned long long pdmca; /* +200 */
|
||||
volatile unsigned long long pdmga;
|
||||
volatile unsigned long long pdmpa;
|
||||
volatile unsigned long long pdmctr;
|
||||
volatile unsigned long long pdmcfg; /* +220 */
|
||||
volatile unsigned long long pdmsts;
|
||||
};
|
||||
|
||||
struct tx4938_aclc_reg {
|
||||
volatile unsigned long acctlen;
|
||||
volatile unsigned long acctldis;
|
||||
|
|
@ -262,18 +200,18 @@ struct tx4938_sramc_reg {
|
|||
};
|
||||
|
||||
struct tx4938_ccfg_reg {
|
||||
volatile unsigned long long ccfg;
|
||||
volatile unsigned long long crir;
|
||||
volatile unsigned long long pcfg;
|
||||
volatile unsigned long long tear;
|
||||
volatile unsigned long long clkctr;
|
||||
volatile unsigned long long unused0;
|
||||
volatile unsigned long long garbc;
|
||||
volatile unsigned long long unused1;
|
||||
volatile unsigned long long unused2;
|
||||
volatile unsigned long long ramp;
|
||||
volatile unsigned long long unused3;
|
||||
volatile unsigned long long jmpadr;
|
||||
u64 ccfg;
|
||||
u64 crir;
|
||||
u64 pcfg;
|
||||
u64 toea;
|
||||
u64 clkctr;
|
||||
u64 unused0;
|
||||
u64 garbc;
|
||||
u64 unused1;
|
||||
u64 unused2;
|
||||
u64 ramp;
|
||||
u64 unused3;
|
||||
u64 jmpadr;
|
||||
};
|
||||
|
||||
#undef endian_def_l2
|
||||
|
|
@ -282,8 +220,6 @@ struct tx4938_ccfg_reg {
|
|||
#undef endian_def_b2s
|
||||
#undef endian_def_b4
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* NDFMC
|
||||
*/
|
||||
|
|
@ -360,7 +296,7 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_CCFG_BEOW 0x00010000
|
||||
#define TX4938_CCFG_WR 0x00008000
|
||||
#define TX4938_CCFG_TOE 0x00004000
|
||||
#define TX4938_CCFG_PCIXARB 0x00002000
|
||||
#define TX4938_CCFG_PCIARB 0x00002000
|
||||
#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
|
||||
#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
|
||||
#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
|
||||
|
|
@ -436,110 +372,6 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_CLKCTR_SIO0RST 0x00000002
|
||||
#define TX4938_CLKCTR_SIO1RST 0x00000001
|
||||
|
||||
/* bits for G2PSTATUS/G2PMASK */
|
||||
#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003
|
||||
#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002
|
||||
#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001
|
||||
|
||||
/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
|
||||
#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900
|
||||
|
||||
/* bits for PBACFG */
|
||||
#define TX4938_PCIC_PBACFG_FIXPA 0x00000008
|
||||
#define TX4938_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4938_PCIC_PBACFG_PBAEN 0x00000002
|
||||
#define TX4938_PCIC_PBACFG_BMCEN 0x00000001
|
||||
|
||||
/* bits for G2PMnGBASE */
|
||||
#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for G2PIOGBASE */
|
||||
#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for PCICSTATUS/PCICMASK */
|
||||
#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8
|
||||
#define TX4938_PCIC_PCICSTATUS_PME 0x00000400
|
||||
#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200
|
||||
#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100
|
||||
#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080
|
||||
#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020
|
||||
#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010
|
||||
#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008
|
||||
#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002
|
||||
#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001
|
||||
|
||||
/* bits for PCICCFG */
|
||||
#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
|
||||
#define TX4938_PCIC_PCICCFG_HRST 0x00000800
|
||||
#define TX4938_PCIC_PCICCFG_SRST 0x00000400
|
||||
#define TX4938_PCIC_PCICCFG_IRBER 0x00000200
|
||||
#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
|
||||
#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100
|
||||
#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080
|
||||
#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040
|
||||
#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020
|
||||
#define TX4938_PCIC_PCICCFG_TCAR 0x00000010
|
||||
#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008
|
||||
|
||||
/* bits for P2GMnGBASE */
|
||||
#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
|
||||
#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for P2GIOGBASE */
|
||||
#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
|
||||
#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
|
||||
|
||||
#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
|
||||
#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
|
||||
|
||||
/* bits for PDMCFG */
|
||||
#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000
|
||||
#define TX4938_PCIC_PDMCFG_EXFER 0x00100000
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400
|
||||
#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200
|
||||
#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100
|
||||
#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080
|
||||
#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040
|
||||
#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
|
||||
#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002
|
||||
#define TX4938_PCIC_PDMCFG_CHRST 0x00000001
|
||||
|
||||
/* bits for PDMSTS */
|
||||
#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
|
||||
#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
|
||||
#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
|
||||
#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000
|
||||
#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800
|
||||
#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400
|
||||
#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200
|
||||
#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100
|
||||
#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080
|
||||
#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040
|
||||
#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020
|
||||
#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008
|
||||
#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004
|
||||
#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002
|
||||
#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001
|
||||
#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0
|
||||
#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f
|
||||
|
||||
/*
|
||||
* DMA
|
||||
*/
|
||||
|
|
@ -595,15 +427,15 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_DMA_CSR_DESERR 0x00000002
|
||||
#define TX4938_DMA_CSR_SORERR 0x00000001
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
|
||||
#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
|
||||
#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
|
||||
#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
|
||||
#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
|
||||
#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
|
||||
#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
|
||||
#define tx4938_pcicptr tx4927_pcicptr
|
||||
#define tx4938_pcic1ptr \
|
||||
((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
|
||||
#define tx4938_ccfgptr \
|
||||
((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
|
||||
#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
|
||||
#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
|
||||
#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
|
||||
|
|
@ -611,17 +443,25 @@ struct tx4938_ccfg_reg {
|
|||
#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
|
||||
|
||||
|
||||
#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
|
||||
#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16)
|
||||
#define TX4938_REV_PCODE() \
|
||||
((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
|
||||
|
||||
#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
|
||||
#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
|
||||
#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
|
||||
|
||||
#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
|
||||
#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
|
||||
|
||||
#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)])
|
||||
#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
|
||||
#define TX4938_EBUSC_SIZE(ch) \
|
||||
(0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
|
||||
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
int tx4938_report_pciclk(void);
|
||||
void tx4938_report_pci1clk(void);
|
||||
int tx4938_pciclk66_setup(void);
|
||||
struct pci_dev;
|
||||
int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue