mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
Merge remote-tracking branches 'spi/topic/pxa2xx', 'spi/topic/qspi', 'spi/topic/s3c24xx', 'spi/topic/s3c64xx', 'spi/topic/sh', 'spi/topic/tegra114', 'spi/topic/tegra20-sflash', 'spi/topic/tegra20-slink', 'spi/topic/txx9' and 'spi/topic/xcomm' into spi-linus
This commit is contained in:
Mark Brown
parent
907e26b6f5
382cebb02a
5a33d30ff1
85a9012446
3e83c19497
909e709c77
48c3fc9380
a553a31d9f
5fd38677a4
bdf0290ac7
4cc16085c8
commit
8aeab58e56
24 changed files with 501 additions and 1156 deletions
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@ -402,7 +402,7 @@ config SPI_S3C24XX_FIQ
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config SPI_S3C64XX
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tristate "Samsung S3C64XX series type SPI"
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depends on PLAT_SAMSUNG
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select S3C64XX_DMA if ARCH_S3C64XX
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select S3C64XX_PL080 if ARCH_S3C64XX
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help
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SPI driver for Samsung S3C64XX and newer SoCs.
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@ -1268,7 +1268,7 @@ static void pxa2xx_spi_shutdown(struct platform_device *pdev)
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dev_err(&pdev->dev, "shutdown failed with %d\n", status);
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}
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM_SLEEP
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static int pxa2xx_spi_suspend(struct device *dev)
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{
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struct driver_data *drv_data = dev_get_drvdata(dev);
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@ -29,7 +29,6 @@
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#include <plat/regs-spi.h>
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#include <plat/fiq.h>
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#include <asm/fiq.h>
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#include "spi-s3c24xx-fiq.h"
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@ -78,14 +77,12 @@ struct s3c24xx_spi {
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unsigned char *rx;
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struct clk *clk;
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struct resource *ioarea;
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struct spi_master *master;
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struct spi_device *curdev;
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struct device *dev;
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struct s3c2410_spi_info *pdata;
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};
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#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
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#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
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@ -517,8 +514,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
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master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
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if (master == NULL) {
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dev_err(&pdev->dev, "No memory for spi_master\n");
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err = -ENOMEM;
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goto err_nomem;
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return -ENOMEM;
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}
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hw = spi_master_get_devdata(master);
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@ -562,48 +558,32 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
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dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
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/* find and map our resources */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
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err = -ENOENT;
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goto err_no_iores;
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}
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hw->ioarea = request_mem_region(res->start, resource_size(res),
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pdev->name);
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if (hw->ioarea == NULL) {
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dev_err(&pdev->dev, "Cannot reserve region\n");
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err = -ENXIO;
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goto err_no_iores;
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}
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hw->regs = ioremap(res->start, resource_size(res));
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if (hw->regs == NULL) {
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dev_err(&pdev->dev, "Cannot map IO\n");
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err = -ENXIO;
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goto err_no_iomap;
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hw->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(hw->regs)) {
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err = PTR_ERR(hw->regs);
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goto err_no_pdata;
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}
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hw->irq = platform_get_irq(pdev, 0);
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if (hw->irq < 0) {
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dev_err(&pdev->dev, "No IRQ specified\n");
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err = -ENOENT;
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goto err_no_irq;
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goto err_no_pdata;
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}
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err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
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err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
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pdev->name, hw);
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if (err) {
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dev_err(&pdev->dev, "Cannot claim IRQ\n");
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goto err_no_irq;
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goto err_no_pdata;
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}
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hw->clk = clk_get(&pdev->dev, "spi");
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hw->clk = devm_clk_get(&pdev->dev, "spi");
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if (IS_ERR(hw->clk)) {
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dev_err(&pdev->dev, "No clock for device\n");
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err = PTR_ERR(hw->clk);
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goto err_no_clk;
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goto err_no_pdata;
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}
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/* setup any gpio we can */
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@ -615,7 +595,8 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
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goto err_register;
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}
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err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
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err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
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dev_name(&pdev->dev));
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if (err) {
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dev_err(&pdev->dev, "Failed to get gpio for cs\n");
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goto err_register;
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@ -639,27 +620,10 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
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return 0;
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err_register:
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if (hw->set_cs == s3c24xx_spi_gpiocs)
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gpio_free(pdata->pin_cs);
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clk_disable(hw->clk);
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clk_put(hw->clk);
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err_no_clk:
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free_irq(hw->irq, hw);
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err_no_irq:
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iounmap(hw->regs);
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err_no_iomap:
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release_resource(hw->ioarea);
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kfree(hw->ioarea);
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err_no_iores:
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err_no_pdata:
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spi_master_put(hw->master);
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err_nomem:
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return err;
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}
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@ -668,19 +632,7 @@ static int s3c24xx_spi_remove(struct platform_device *dev)
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struct s3c24xx_spi *hw = platform_get_drvdata(dev);
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spi_bitbang_stop(&hw->bitbang);
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clk_disable(hw->clk);
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clk_put(hw->clk);
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free_irq(hw->irq, hw);
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iounmap(hw->regs);
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if (hw->set_cs == s3c24xx_spi_gpiocs)
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gpio_free(hw->pdata->pin_cs);
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release_resource(hw->ioarea);
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kfree(hw->ioarea);
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spi_master_put(hw->master);
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return 0;
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}
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@ -890,7 +890,7 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
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unsigned long flags;
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int use_dma;
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reinit_completion(&sdd->xfer_completion);
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reinit_completion(&sdd->xfer_completion);
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/* Only BPW and Speed may change across transfers */
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bpw = xfer->bits_per_word;
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@ -927,9 +927,6 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
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/* Start the signals */
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writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
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/* Start the signals */
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writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
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spin_unlock_irqrestore(&sdd->lock, flags);
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status = wait_for_xfer(sdd, xfer, use_dma);
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@ -171,7 +171,6 @@ static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
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int remain = t->len;
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int cur_len;
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unsigned char *data;
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unsigned long tmp;
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long ret;
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if (t->len)
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@ -213,9 +212,7 @@ static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
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}
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if (list_is_last(&t->transfer_list, &mesg->transfers)) {
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tmp = spi_sh_read(ss, SPI_SH_CR1);
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tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
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spi_sh_write(ss, tmp, SPI_SH_CR1);
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spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
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ss->cr1 &= ~SPI_SH_TBE;
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@ -239,7 +236,6 @@ static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
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int remain = t->len;
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int cur_len;
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unsigned char *data;
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unsigned long tmp;
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long ret;
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if (t->len > SPI_SH_MAX_BYTE)
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@ -247,9 +243,7 @@ static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
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else
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spi_sh_write(ss, t->len, SPI_SH_CR3);
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tmp = spi_sh_read(ss, SPI_SH_CR1);
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tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
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spi_sh_write(ss, tmp, SPI_SH_CR1);
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spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
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spi_sh_wait_write_buffer_empty(ss);
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@ -54,11 +54,8 @@
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#define SPI_CS_SS_VAL (1 << 20)
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#define SPI_CS_SW_HW (1 << 21)
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/* SPI_CS_POL_INACTIVE bits are default high */
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#define SPI_CS_POL_INACTIVE 22
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#define SPI_CS_POL_INACTIVE_0 (1 << 22)
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#define SPI_CS_POL_INACTIVE_1 (1 << 23)
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#define SPI_CS_POL_INACTIVE_2 (1 << 24)
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#define SPI_CS_POL_INACTIVE_3 (1 << 25)
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/* n from 0 to 3 */
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#define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
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#define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
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#define SPI_CS_SEL_0 (0 << 26)
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@ -165,9 +162,6 @@
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#define MAX_HOLD_CYCLES 16
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#define SPI_DEFAULT_SPEED 25000000
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#define MAX_CHIP_SELECT 4
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#define SPI_FIFO_DEPTH 64
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struct tegra_spi_data {
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struct device *dev;
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struct spi_master *master;
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@ -184,7 +178,6 @@ struct tegra_spi_data {
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struct spi_device *cur_spi;
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struct spi_device *cs_control;
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unsigned cur_pos;
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unsigned cur_len;
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unsigned words_per_32bit;
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unsigned bytes_per_word;
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unsigned curr_dma_words;
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@ -204,12 +197,10 @@ struct tegra_spi_data {
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u32 rx_status;
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u32 status_reg;
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bool is_packed;
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unsigned long packed_size;
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u32 command1_reg;
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u32 dma_control_reg;
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u32 def_command1_reg;
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u32 spi_cs_timing;
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struct completion xfer_completion;
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struct spi_transfer *curr_xfer;
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@ -227,14 +218,14 @@ struct tegra_spi_data {
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static int tegra_spi_runtime_suspend(struct device *dev);
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static int tegra_spi_runtime_resume(struct device *dev);
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static inline unsigned long tegra_spi_readl(struct tegra_spi_data *tspi,
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static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
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unsigned long reg)
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{
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return readl(tspi->base + reg);
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}
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static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
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unsigned long val, unsigned long reg)
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u32 val, unsigned long reg)
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{
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writel(val, tspi->base + reg);
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@ -245,7 +236,7 @@ static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
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static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
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{
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unsigned long val;
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u32 val;
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/* Write 1 to clear status register */
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val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
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@ -296,10 +287,9 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
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{
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unsigned nbytes;
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unsigned tx_empty_count;
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unsigned long fifo_status;
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u32 fifo_status;
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unsigned max_n_32bit;
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unsigned i, count;
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unsigned long x;
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unsigned int written_words;
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unsigned fifo_words_left;
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u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
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@ -313,9 +303,9 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
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nbytes = written_words * tspi->bytes_per_word;
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max_n_32bit = DIV_ROUND_UP(nbytes, 4);
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for (count = 0; count < max_n_32bit; count++) {
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x = 0;
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u32 x = 0;
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for (i = 0; (i < 4) && nbytes; i++, nbytes--)
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x |= (*tx_buf++) << (i*8);
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x |= (u32)(*tx_buf++) << (i * 8);
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tegra_spi_writel(tspi, x, SPI_TX_FIFO);
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}
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} else {
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@ -323,10 +313,10 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
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written_words = max_n_32bit;
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nbytes = written_words * tspi->bytes_per_word;
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for (count = 0; count < max_n_32bit; count++) {
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x = 0;
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u32 x = 0;
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for (i = 0; nbytes && (i < tspi->bytes_per_word);
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i++, nbytes--)
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x |= ((*tx_buf++) << i*8);
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x |= (u32)(*tx_buf++) << (i * 8);
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tegra_spi_writel(tspi, x, SPI_TX_FIFO);
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}
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}
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@ -338,9 +328,8 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
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struct tegra_spi_data *tspi, struct spi_transfer *t)
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{
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unsigned rx_full_count;
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unsigned long fifo_status;
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u32 fifo_status;
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unsigned i, count;
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unsigned long x;
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unsigned int read_words = 0;
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unsigned len;
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u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
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@ -350,20 +339,16 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
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if (tspi->is_packed) {
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len = tspi->curr_dma_words * tspi->bytes_per_word;
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for (count = 0; count < rx_full_count; count++) {
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x = tegra_spi_readl(tspi, SPI_RX_FIFO);
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u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
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for (i = 0; len && (i < 4); i++, len--)
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*rx_buf++ = (x >> i*8) & 0xFF;
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}
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tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
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read_words += tspi->curr_dma_words;
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} else {
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unsigned int rx_mask;
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unsigned int bits_per_word = t->bits_per_word;
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rx_mask = (1 << bits_per_word) - 1;
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u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
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for (count = 0; count < rx_full_count; count++) {
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x = tegra_spi_readl(tspi, SPI_RX_FIFO);
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x &= rx_mask;
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u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
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for (i = 0; (i < tspi->bytes_per_word); i++)
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*rx_buf++ = (x >> (i*8)) & 0xFF;
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}
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@ -376,27 +361,24 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
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static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
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struct tegra_spi_data *tspi, struct spi_transfer *t)
|
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{
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unsigned len;
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|
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/* Make the dma buffer to read by cpu */
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dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
|
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tspi->dma_buf_size, DMA_TO_DEVICE);
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|
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if (tspi->is_packed) {
|
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len = tspi->curr_dma_words * tspi->bytes_per_word;
|
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unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
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memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
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} else {
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unsigned int i;
|
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unsigned int count;
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u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
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unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
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unsigned int x;
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for (count = 0; count < tspi->curr_dma_words; count++) {
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x = 0;
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u32 x = 0;
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for (i = 0; consume && (i < tspi->bytes_per_word);
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i++, consume--)
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x |= ((*tx_buf++) << i * 8);
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x |= (u32)(*tx_buf++) << (i * 8);
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tspi->tx_dma_buf[count] = x;
|
||||
}
|
||||
}
|
||||
|
|
@ -410,27 +392,21 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
|
|||
static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
|
||||
struct tegra_spi_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned len;
|
||||
|
||||
/* Make the dma buffer to read by cpu */
|
||||
dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
|
||||
tspi->dma_buf_size, DMA_FROM_DEVICE);
|
||||
|
||||
if (tspi->is_packed) {
|
||||
len = tspi->curr_dma_words * tspi->bytes_per_word;
|
||||
unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
|
||||
memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
|
||||
} else {
|
||||
unsigned int i;
|
||||
unsigned int count;
|
||||
unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
|
||||
unsigned int x;
|
||||
unsigned int rx_mask;
|
||||
unsigned int bits_per_word = t->bits_per_word;
|
||||
u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
|
||||
|
||||
rx_mask = (1 << bits_per_word) - 1;
|
||||
for (count = 0; count < tspi->curr_dma_words; count++) {
|
||||
x = tspi->rx_dma_buf[count];
|
||||
x &= rx_mask;
|
||||
u32 x = tspi->rx_dma_buf[count] & rx_mask;
|
||||
for (i = 0; (i < tspi->bytes_per_word); i++)
|
||||
*rx_buf++ = (x >> (i*8)) & 0xFF;
|
||||
}
|
||||
|
|
@ -490,16 +466,16 @@ static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
|
|||
static int tegra_spi_start_dma_based_transfer(
|
||||
struct tegra_spi_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned long val;
|
||||
u32 val;
|
||||
unsigned int len;
|
||||
int ret = 0;
|
||||
unsigned long status;
|
||||
u32 status;
|
||||
|
||||
/* Make sure that Rx and Tx fifo are empty */
|
||||
status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
|
||||
if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
|
||||
dev_err(tspi->dev,
|
||||
"Rx/Tx fifo are not empty status 0x%08lx\n", status);
|
||||
dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
|
||||
(unsigned)status);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
@ -564,7 +540,7 @@ static int tegra_spi_start_dma_based_transfer(
|
|||
static int tegra_spi_start_cpu_based_transfer(
|
||||
struct tegra_spi_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned long val;
|
||||
u32 val;
|
||||
unsigned cur_words;
|
||||
|
||||
if (tspi->cur_direction & DATA_DIR_TX)
|
||||
|
|
@ -677,13 +653,13 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
|
|||
dma_release_channel(dma_chan);
|
||||
}
|
||||
|
||||
static unsigned long tegra_spi_setup_transfer_one(struct spi_device *spi,
|
||||
static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
|
||||
struct spi_transfer *t, bool is_first_of_msg)
|
||||
{
|
||||
struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
|
||||
u32 speed = t->speed_hz;
|
||||
u8 bits_per_word = t->bits_per_word;
|
||||
unsigned long command1;
|
||||
u32 command1;
|
||||
int req_mode;
|
||||
|
||||
if (speed != tspi->cur_speed) {
|
||||
|
|
@ -738,7 +714,7 @@ static unsigned long tegra_spi_setup_transfer_one(struct spi_device *spi,
|
|||
}
|
||||
|
||||
static int tegra_spi_start_transfer_one(struct spi_device *spi,
|
||||
struct spi_transfer *t, unsigned long command1)
|
||||
struct spi_transfer *t, u32 command1)
|
||||
{
|
||||
struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
|
||||
unsigned total_fifo_words;
|
||||
|
|
@ -763,8 +739,8 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
|
|||
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
|
||||
tspi->command1_reg = command1;
|
||||
|
||||
dev_dbg(tspi->dev, "The def 0x%x and written 0x%lx\n",
|
||||
tspi->def_command1_reg, command1);
|
||||
dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
|
||||
tspi->def_command1_reg, (unsigned)command1);
|
||||
|
||||
if (total_fifo_words > SPI_FIFO_DEPTH)
|
||||
ret = tegra_spi_start_dma_based_transfer(tspi, t);
|
||||
|
|
@ -776,15 +752,9 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
|
|||
static int tegra_spi_setup(struct spi_device *spi)
|
||||
{
|
||||
struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
|
||||
unsigned long val;
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
|
||||
SPI_CS_POL_INACTIVE_0,
|
||||
SPI_CS_POL_INACTIVE_1,
|
||||
SPI_CS_POL_INACTIVE_2,
|
||||
SPI_CS_POL_INACTIVE_3,
|
||||
};
|
||||
|
||||
dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
|
||||
spi->bits_per_word,
|
||||
|
|
@ -806,9 +776,9 @@ static int tegra_spi_setup(struct spi_device *spi)
|
|||
spin_lock_irqsave(&tspi->lock, flags);
|
||||
val = tspi->def_command1_reg;
|
||||
if (spi->mode & SPI_CS_HIGH)
|
||||
val &= ~cs_pol_bit[spi->chip_select];
|
||||
val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
|
||||
else
|
||||
val |= cs_pol_bit[spi->chip_select];
|
||||
val |= SPI_CS_POL_INACTIVE(spi->chip_select);
|
||||
tspi->def_command1_reg = val;
|
||||
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
|
||||
spin_unlock_irqrestore(&tspi->lock, flags);
|
||||
|
|
@ -842,7 +812,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
|
|||
msg->actual_length = 0;
|
||||
|
||||
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
||||
unsigned long cmd1;
|
||||
u32 cmd1;
|
||||
|
||||
reinit_completion(&tspi->xfer_completion);
|
||||
|
||||
|
|
|
|||
|
|
@ -148,14 +148,14 @@ struct tegra_sflash_data {
|
|||
static int tegra_sflash_runtime_suspend(struct device *dev);
|
||||
static int tegra_sflash_runtime_resume(struct device *dev);
|
||||
|
||||
static inline unsigned long tegra_sflash_readl(struct tegra_sflash_data *tsd,
|
||||
static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
|
||||
unsigned long reg)
|
||||
{
|
||||
return readl(tsd->base + reg);
|
||||
}
|
||||
|
||||
static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
|
||||
unsigned long val, unsigned long reg)
|
||||
u32 val, unsigned long reg)
|
||||
{
|
||||
writel(val, tsd->base + reg);
|
||||
}
|
||||
|
|
@ -185,7 +185,7 @@ static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
|
|||
struct tegra_sflash_data *tsd, struct spi_transfer *t)
|
||||
{
|
||||
unsigned nbytes;
|
||||
unsigned long status;
|
||||
u32 status;
|
||||
unsigned max_n_32bit = tsd->curr_xfer_words;
|
||||
u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
|
||||
|
||||
|
|
@ -196,11 +196,11 @@ static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
|
|||
status = tegra_sflash_readl(tsd, SPI_STATUS);
|
||||
while (!(status & SPI_TXF_FULL)) {
|
||||
int i;
|
||||
unsigned int x = 0;
|
||||
u32 x = 0;
|
||||
|
||||
for (i = 0; nbytes && (i < tsd->bytes_per_word);
|
||||
i++, nbytes--)
|
||||
x |= ((*tx_buf++) << i*8);
|
||||
x |= (u32)(*tx_buf++) << (i * 8);
|
||||
tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
|
||||
if (!nbytes)
|
||||
break;
|
||||
|
|
@ -214,16 +214,14 @@ static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
|
|||
static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
|
||||
struct tegra_sflash_data *tsd, struct spi_transfer *t)
|
||||
{
|
||||
unsigned long status;
|
||||
u32 status;
|
||||
unsigned int read_words = 0;
|
||||
u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
|
||||
|
||||
status = tegra_sflash_readl(tsd, SPI_STATUS);
|
||||
while (!(status & SPI_RXF_EMPTY)) {
|
||||
int i;
|
||||
unsigned long x;
|
||||
|
||||
x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
|
||||
u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
|
||||
for (i = 0; (i < tsd->bytes_per_word); i++)
|
||||
*rx_buf++ = (x >> (i*8)) & 0xFF;
|
||||
read_words++;
|
||||
|
|
@ -236,7 +234,7 @@ static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
|
|||
static int tegra_sflash_start_cpu_based_transfer(
|
||||
struct tegra_sflash_data *tsd, struct spi_transfer *t)
|
||||
{
|
||||
unsigned long val = 0;
|
||||
u32 val = 0;
|
||||
unsigned cur_words;
|
||||
|
||||
if (tsd->cur_direction & DATA_DIR_TX)
|
||||
|
|
@ -266,7 +264,7 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi,
|
|||
{
|
||||
struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
|
||||
u32 speed;
|
||||
unsigned long command;
|
||||
u32 command;
|
||||
|
||||
speed = t->speed_hz;
|
||||
if (speed != tsd->cur_speed) {
|
||||
|
|
@ -313,7 +311,7 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi,
|
|||
tegra_sflash_writel(tsd, command, SPI_COMMAND);
|
||||
tsd->command_reg = command;
|
||||
|
||||
return tegra_sflash_start_cpu_based_transfer(tsd, t);
|
||||
return tegra_sflash_start_cpu_based_transfer(tsd, t);
|
||||
}
|
||||
|
||||
static int tegra_sflash_setup(struct spi_device *spi)
|
||||
|
|
|
|||
|
|
@ -196,7 +196,7 @@ struct tegra_slink_data {
|
|||
u32 rx_status;
|
||||
u32 status_reg;
|
||||
bool is_packed;
|
||||
unsigned long packed_size;
|
||||
u32 packed_size;
|
||||
|
||||
u32 command_reg;
|
||||
u32 command2_reg;
|
||||
|
|
@ -220,14 +220,14 @@ struct tegra_slink_data {
|
|||
static int tegra_slink_runtime_suspend(struct device *dev);
|
||||
static int tegra_slink_runtime_resume(struct device *dev);
|
||||
|
||||
static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi,
|
||||
static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
|
||||
unsigned long reg)
|
||||
{
|
||||
return readl(tspi->base + reg);
|
||||
}
|
||||
|
||||
static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
|
||||
unsigned long val, unsigned long reg)
|
||||
u32 val, unsigned long reg)
|
||||
{
|
||||
writel(val, tspi->base + reg);
|
||||
|
||||
|
|
@ -238,38 +238,30 @@ static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
|
|||
|
||||
static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned long val_write = 0;
|
||||
u32 val_write;
|
||||
|
||||
val = tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
|
||||
/* Write 1 to clear status register */
|
||||
val_write = SLINK_RDY | SLINK_FIFO_ERROR;
|
||||
tegra_slink_writel(tspi, val_write, SLINK_STATUS);
|
||||
}
|
||||
|
||||
static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
|
||||
static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
|
||||
struct spi_transfer *t)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
switch (tspi->bytes_per_word) {
|
||||
case 0:
|
||||
val = SLINK_PACK_SIZE_4;
|
||||
break;
|
||||
return SLINK_PACK_SIZE_4;
|
||||
case 1:
|
||||
val = SLINK_PACK_SIZE_8;
|
||||
break;
|
||||
return SLINK_PACK_SIZE_8;
|
||||
case 2:
|
||||
val = SLINK_PACK_SIZE_16;
|
||||
break;
|
||||
return SLINK_PACK_SIZE_16;
|
||||
case 4:
|
||||
val = SLINK_PACK_SIZE_32;
|
||||
break;
|
||||
return SLINK_PACK_SIZE_32;
|
||||
default:
|
||||
val = 0;
|
||||
return 0;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
static unsigned tegra_slink_calculate_curr_xfer_param(
|
||||
|
|
@ -312,10 +304,9 @@ static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
|
|||
{
|
||||
unsigned nbytes;
|
||||
unsigned tx_empty_count;
|
||||
unsigned long fifo_status;
|
||||
u32 fifo_status;
|
||||
unsigned max_n_32bit;
|
||||
unsigned i, count;
|
||||
unsigned long x;
|
||||
unsigned int written_words;
|
||||
unsigned fifo_words_left;
|
||||
u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
|
||||
|
|
@ -329,9 +320,9 @@ static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
|
|||
nbytes = written_words * tspi->bytes_per_word;
|
||||
max_n_32bit = DIV_ROUND_UP(nbytes, 4);
|
||||
for (count = 0; count < max_n_32bit; count++) {
|
||||
x = 0;
|
||||
u32 x = 0;
|
||||
for (i = 0; (i < 4) && nbytes; i++, nbytes--)
|
||||
x |= (*tx_buf++) << (i*8);
|
||||
x |= (u32)(*tx_buf++) << (i * 8);
|
||||
tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
|
||||
}
|
||||
} else {
|
||||
|
|
@ -339,10 +330,10 @@ static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
|
|||
written_words = max_n_32bit;
|
||||
nbytes = written_words * tspi->bytes_per_word;
|
||||
for (count = 0; count < max_n_32bit; count++) {
|
||||
x = 0;
|
||||
u32 x = 0;
|
||||
for (i = 0; nbytes && (i < tspi->bytes_per_word);
|
||||
i++, nbytes--)
|
||||
x |= ((*tx_buf++) << i*8);
|
||||
x |= (u32)(*tx_buf++) << (i * 8);
|
||||
tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
|
||||
}
|
||||
}
|
||||
|
|
@ -354,9 +345,8 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
|
|||
struct tegra_slink_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned rx_full_count;
|
||||
unsigned long fifo_status;
|
||||
u32 fifo_status;
|
||||
unsigned i, count;
|
||||
unsigned long x;
|
||||
unsigned int read_words = 0;
|
||||
unsigned len;
|
||||
u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
|
||||
|
|
@ -366,7 +356,7 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
|
|||
if (tspi->is_packed) {
|
||||
len = tspi->curr_dma_words * tspi->bytes_per_word;
|
||||
for (count = 0; count < rx_full_count; count++) {
|
||||
x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
|
||||
u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
|
||||
for (i = 0; len && (i < 4); i++, len--)
|
||||
*rx_buf++ = (x >> i*8) & 0xFF;
|
||||
}
|
||||
|
|
@ -374,7 +364,7 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
|
|||
read_words += tspi->curr_dma_words;
|
||||
} else {
|
||||
for (count = 0; count < rx_full_count; count++) {
|
||||
x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
|
||||
u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
|
||||
for (i = 0; (i < tspi->bytes_per_word); i++)
|
||||
*rx_buf++ = (x >> (i*8)) & 0xFF;
|
||||
}
|
||||
|
|
@ -387,27 +377,24 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
|
|||
static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
|
||||
struct tegra_slink_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned len;
|
||||
|
||||
/* Make the dma buffer to read by cpu */
|
||||
dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
|
||||
tspi->dma_buf_size, DMA_TO_DEVICE);
|
||||
|
||||
if (tspi->is_packed) {
|
||||
len = tspi->curr_dma_words * tspi->bytes_per_word;
|
||||
unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
|
||||
memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
|
||||
} else {
|
||||
unsigned int i;
|
||||
unsigned int count;
|
||||
u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
|
||||
unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
|
||||
unsigned int x;
|
||||
|
||||
for (count = 0; count < tspi->curr_dma_words; count++) {
|
||||
x = 0;
|
||||
u32 x = 0;
|
||||
for (i = 0; consume && (i < tspi->bytes_per_word);
|
||||
i++, consume--)
|
||||
x |= ((*tx_buf++) << i * 8);
|
||||
x |= (u32)(*tx_buf++) << (i * 8);
|
||||
tspi->tx_dma_buf[count] = x;
|
||||
}
|
||||
}
|
||||
|
|
@ -434,14 +421,10 @@ static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
|
|||
unsigned int i;
|
||||
unsigned int count;
|
||||
unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
|
||||
unsigned int x;
|
||||
unsigned int rx_mask, bits_per_word;
|
||||
u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
|
||||
|
||||
bits_per_word = t->bits_per_word;
|
||||
rx_mask = (1 << bits_per_word) - 1;
|
||||
for (count = 0; count < tspi->curr_dma_words; count++) {
|
||||
x = tspi->rx_dma_buf[count];
|
||||
x &= rx_mask;
|
||||
u32 x = tspi->rx_dma_buf[count] & rx_mask;
|
||||
for (i = 0; (i < tspi->bytes_per_word); i++)
|
||||
*rx_buf++ = (x >> (i*8)) & 0xFF;
|
||||
}
|
||||
|
|
@ -501,17 +484,16 @@ static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
|
|||
static int tegra_slink_start_dma_based_transfer(
|
||||
struct tegra_slink_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned long test_val;
|
||||
u32 val;
|
||||
unsigned int len;
|
||||
int ret = 0;
|
||||
unsigned long status;
|
||||
u32 status;
|
||||
|
||||
/* Make sure that Rx and Tx fifo are empty */
|
||||
status = tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
|
||||
dev_err(tspi->dev,
|
||||
"Rx/Tx fifo are not empty status 0x%08lx\n", status);
|
||||
dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
|
||||
(unsigned)status);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
@ -551,9 +533,9 @@ static int tegra_slink_start_dma_based_transfer(
|
|||
}
|
||||
|
||||
/* Wait for tx fifo to be fill before starting slink */
|
||||
test_val = tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
while (!(test_val & SLINK_TX_FULL))
|
||||
test_val = tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
status = tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
while (!(status & SLINK_TX_FULL))
|
||||
status = tegra_slink_readl(tspi, SLINK_STATUS);
|
||||
}
|
||||
|
||||
if (tspi->cur_direction & DATA_DIR_RX) {
|
||||
|
|
@ -587,7 +569,7 @@ static int tegra_slink_start_dma_based_transfer(
|
|||
static int tegra_slink_start_cpu_based_transfer(
|
||||
struct tegra_slink_data *tspi, struct spi_transfer *t)
|
||||
{
|
||||
unsigned long val;
|
||||
u32 val;
|
||||
unsigned cur_words;
|
||||
|
||||
val = tspi->packed_size;
|
||||
|
|
@ -714,8 +696,8 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi,
|
|||
u8 bits_per_word;
|
||||
unsigned total_fifo_words;
|
||||
int ret;
|
||||
unsigned long command;
|
||||
unsigned long command2;
|
||||
u32 command;
|
||||
u32 command2;
|
||||
|
||||
bits_per_word = t->bits_per_word;
|
||||
speed = t->speed_hz;
|
||||
|
|
@ -762,17 +744,18 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi,
|
|||
|
||||
static int tegra_slink_setup(struct spi_device *spi)
|
||||
{
|
||||
struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
|
||||
unsigned long val;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
|
||||
static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
|
||||
SLINK_CS_POLARITY,
|
||||
SLINK_CS_POLARITY1,
|
||||
SLINK_CS_POLARITY2,
|
||||
SLINK_CS_POLARITY3,
|
||||
};
|
||||
|
||||
struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
|
||||
spi->bits_per_word,
|
||||
spi->mode & SPI_CPOL ? "" : "~",
|
||||
|
|
|
|||
|
|
@ -46,6 +46,8 @@ struct ti_qspi {
|
|||
|
||||
struct spi_master *master;
|
||||
void __iomem *base;
|
||||
void __iomem *ctrl_base;
|
||||
void __iomem *mmap_base;
|
||||
struct clk *fclk;
|
||||
struct device *dev;
|
||||
|
||||
|
|
@ -54,6 +56,8 @@ struct ti_qspi {
|
|||
u32 spi_max_frequency;
|
||||
u32 cmd;
|
||||
u32 dc;
|
||||
|
||||
bool ctrl_mod;
|
||||
};
|
||||
|
||||
#define QSPI_PID (0x0)
|
||||
|
|
@ -204,53 +208,36 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||
txbuf = t->tx_buf;
|
||||
cmd = qspi->cmd | QSPI_WR_SNGL;
|
||||
count = t->len;
|
||||
wlen = t->bits_per_word;
|
||||
wlen = t->bits_per_word >> 3; /* in bytes */
|
||||
|
||||
while (count) {
|
||||
switch (wlen) {
|
||||
case 8:
|
||||
case 1:
|
||||
dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
|
||||
cmd, qspi->dc, *txbuf);
|
||||
writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
|
||||
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
||||
ret = wait_for_completion_timeout(&qspi->transfer_complete,
|
||||
QSPI_COMPLETION_TIMEOUT);
|
||||
if (ret == 0) {
|
||||
dev_err(qspi->dev, "write timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
txbuf += 1;
|
||||
count -= 1;
|
||||
break;
|
||||
case 16:
|
||||
case 2:
|
||||
dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
|
||||
cmd, qspi->dc, *txbuf);
|
||||
writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
|
||||
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
||||
ret = wait_for_completion_timeout(&qspi->transfer_complete,
|
||||
QSPI_COMPLETION_TIMEOUT);
|
||||
if (ret == 0) {
|
||||
dev_err(qspi->dev, "write timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
txbuf += 2;
|
||||
count -= 2;
|
||||
break;
|
||||
case 32:
|
||||
case 4:
|
||||
dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
|
||||
cmd, qspi->dc, *txbuf);
|
||||
writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
|
||||
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
||||
ret = wait_for_completion_timeout(&qspi->transfer_complete,
|
||||
QSPI_COMPLETION_TIMEOUT);
|
||||
if (ret == 0) {
|
||||
dev_err(qspi->dev, "write timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
txbuf += 4;
|
||||
count -= 4;
|
||||
break;
|
||||
}
|
||||
|
||||
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
||||
ret = wait_for_completion_timeout(&qspi->transfer_complete,
|
||||
QSPI_COMPLETION_TIMEOUT);
|
||||
if (ret == 0) {
|
||||
dev_err(qspi->dev, "write timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
txbuf += wlen;
|
||||
count -= wlen;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -276,7 +263,7 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||
break;
|
||||
}
|
||||
count = t->len;
|
||||
wlen = t->bits_per_word;
|
||||
wlen = t->bits_per_word >> 3; /* in bytes */
|
||||
|
||||
while (count) {
|
||||
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
|
||||
|
|
@ -288,22 +275,18 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
switch (wlen) {
|
||||
case 8:
|
||||
case 1:
|
||||
*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
|
||||
rxbuf += 1;
|
||||
count -= 1;
|
||||
break;
|
||||
case 16:
|
||||
case 2:
|
||||
*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
|
||||
rxbuf += 2;
|
||||
count -= 2;
|
||||
break;
|
||||
case 32:
|
||||
case 4:
|
||||
*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
|
||||
rxbuf += 4;
|
||||
count -= 4;
|
||||
break;
|
||||
}
|
||||
rxbuf += wlen;
|
||||
count -= wlen;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -435,7 +418,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct ti_qspi *qspi;
|
||||
struct spi_master *master;
|
||||
struct resource *r;
|
||||
struct resource *r, *res_ctrl, *res_mmap;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
u32 max_freq;
|
||||
int ret = 0, num_cs, irq;
|
||||
|
|
@ -462,7 +445,35 @@ static int ti_qspi_probe(struct platform_device *pdev)
|
|||
qspi->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, qspi);
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
|
||||
if (r == NULL) {
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (r == NULL) {
|
||||
dev_err(&pdev->dev, "missing platform data\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
res_mmap = platform_get_resource_byname(pdev,
|
||||
IORESOURCE_MEM, "qspi_mmap");
|
||||
if (res_mmap == NULL) {
|
||||
res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (res_mmap == NULL) {
|
||||
dev_err(&pdev->dev,
|
||||
"memory mapped resource not required\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
res_ctrl = platform_get_resource_byname(pdev,
|
||||
IORESOURCE_MEM, "qspi_ctrlmod");
|
||||
if (res_ctrl == NULL) {
|
||||
res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
if (res_ctrl == NULL) {
|
||||
dev_dbg(&pdev->dev,
|
||||
"control module resources not required\n");
|
||||
}
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
|
|
@ -478,6 +489,23 @@ static int ti_qspi_probe(struct platform_device *pdev)
|
|||
goto free_master;
|
||||
}
|
||||
|
||||
if (res_ctrl) {
|
||||
qspi->ctrl_mod = true;
|
||||
qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
|
||||
if (IS_ERR(qspi->ctrl_base)) {
|
||||
ret = PTR_ERR(qspi->ctrl_base);
|
||||
goto free_master;
|
||||
}
|
||||
}
|
||||
|
||||
if (res_mmap) {
|
||||
qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
|
||||
if (IS_ERR(qspi->mmap_base)) {
|
||||
ret = PTR_ERR(qspi->mmap_base);
|
||||
goto free_master;
|
||||
}
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
|
||||
dev_name(&pdev->dev), qspi);
|
||||
if (ret < 0) {
|
||||
|
|
@ -539,7 +567,7 @@ static struct platform_driver ti_qspi_driver = {
|
|||
.probe = ti_qspi_probe,
|
||||
.remove = ti_qspi_remove,
|
||||
.driver = {
|
||||
.name = "ti,dra7xxx-qspi",
|
||||
.name = "ti-qspi",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &ti_qspi_pm_ops,
|
||||
.of_match_table = ti_qspi_match,
|
||||
|
|
@ -551,3 +579,4 @@ module_platform_driver(ti_qspi_driver);
|
|||
MODULE_AUTHOR("Sourav Poddar <[email protected]>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("TI QSPI controller driver");
|
||||
MODULE_ALIAS("platform:ti-qspi");
|
||||
|
|
|
|||
|
|
@ -348,7 +348,7 @@ static int txx9spi_probe(struct platform_device *dev)
|
|||
INIT_LIST_HEAD(&c->queue);
|
||||
init_waitqueue_head(&c->waitq);
|
||||
|
||||
c->clk = clk_get(&dev->dev, "spi-baseclk");
|
||||
c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
|
||||
if (IS_ERR(c->clk)) {
|
||||
ret = PTR_ERR(c->clk);
|
||||
c->clk = NULL;
|
||||
|
|
@ -356,7 +356,6 @@ static int txx9spi_probe(struct platform_device *dev)
|
|||
}
|
||||
ret = clk_enable(c->clk);
|
||||
if (ret) {
|
||||
clk_put(c->clk);
|
||||
c->clk = NULL;
|
||||
goto exit;
|
||||
}
|
||||
|
|
@ -415,10 +414,8 @@ exit_busy:
|
|||
exit:
|
||||
if (c->workqueue)
|
||||
destroy_workqueue(c->workqueue);
|
||||
if (c->clk) {
|
||||
if (c->clk)
|
||||
clk_disable(c->clk);
|
||||
clk_put(c->clk);
|
||||
}
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -430,7 +427,6 @@ static int txx9spi_remove(struct platform_device *dev)
|
|||
|
||||
destroy_workqueue(c->workqueue);
|
||||
clk_disable(c->clk);
|
||||
clk_put(c->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -231,22 +231,13 @@ static int spi_xcomm_probe(struct i2c_client *i2c,
|
|||
master->dev.of_node = i2c->dev.of_node;
|
||||
i2c_set_clientdata(i2c, master);
|
||||
|
||||
ret = spi_register_master(master);
|
||||
ret = devm_spi_register_master(&i2c->dev, master);
|
||||
if (ret < 0)
|
||||
spi_master_put(master);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_xcomm_remove(struct i2c_client *i2c)
|
||||
{
|
||||
struct spi_master *master = i2c_get_clientdata(i2c);
|
||||
|
||||
spi_unregister_master(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id spi_xcomm_ids[] = {
|
||||
{ "spi-xcomm" },
|
||||
{ },
|
||||
|
|
@ -259,7 +250,6 @@ static struct i2c_driver spi_xcomm_driver = {
|
|||
},
|
||||
.id_table = spi_xcomm_ids,
|
||||
.probe = spi_xcomm_probe,
|
||||
.remove = spi_xcomm_remove,
|
||||
};
|
||||
module_i2c_driver(spi_xcomm_driver);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue