diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi
new file mode 100644
index 000000000000..6b1baacf6a4f
--- /dev/null
+++ b/display/shima-sde-display-common.dtsi
@@ -0,0 +1,140 @@
+#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
+
+&soc {
+	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1920000>;
+			qcom,supply-max-voltage = <1920000>;
+			qcom,supply-enable-load = <60700>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "vdd";
+			qcom,supply-min-voltage = <3000000>;
+			qcom,supply-max-voltage = <3000000>;
+			qcom,supply-enable-load = <30000>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <0>;
+		};
+
+		qcom,panel-supply-entry@2 {
+			reg = <2>;
+			qcom,supply-name = "lab";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <0>;
+			qcom,supply-disable-load = <0>;
+		};
+
+		qcom,panel-supply-entry@3 {
+			reg = <3>;
+			qcom,supply-name = "ibb";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <0>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	sde_dsi: qcom,dsi-display-primary {
+		compatible = "qcom,dsi-display";
+		label = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+		qcom,mdp = <&mdss_mdp>;
+	};
+
+	sde_dsi1: qcom,dsi-display-secondary {
+		compatible = "qcom,dsi-display";
+		label = "secondary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+		qcom,mdp = <&mdss_mdp>;
+	};
+};
+
+&dsi_r66451_amoled_video {
+	qcom,dsi-supported-dfps-list = <120 90 60 48>;
+	qcom,mdss-dsi-pan-enable-dynamic-fps;
+	qcom,mdss-dsi-min-refresh-rate = <48>;
+	qcom,mdss-dsi-max-refresh-rate = <120>;
+	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08
+				08 05 02 04 00 17 0c];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_r66451_amoled_60hz_video {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04
+				04 03 02 04 00 0e 09];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_r66451_amoled_cmd {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
+				04 03 02 04 00 0e 09];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+
+		timing@1 {
+			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
+				06 06 02 04 00 14 0a];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+
+		timing@2 {
+			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
+				07 08 02 04 00 19 0c];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_sim_vid {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
+				01 01 02 04 00 06 06];
+			qcom,display-topology = <1 0 1>,
+						<2 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi
index a4d84a3f6033..b2e706c34a36 100644
--- a/display/shima-sde-display.dtsi
+++ b/display/shima-sde-display.dtsi
@@ -1,134 +1,6 @@
-#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
-#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi"
-#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
-#include "dsi-panel-sim-video.dtsi"
-#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
+#include "shima-sde-display-common.dtsi"
 
 &soc {
-	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		qcom,panel-supply-entry@0 {
-			reg = <0>;
-			qcom,supply-name = "vddio";
-			qcom,supply-min-voltage = <1920000>;
-			qcom,supply-max-voltage = <1920000>;
-			qcom,supply-enable-load = <60700>;
-			qcom,supply-disable-load = <80>;
-			qcom,supply-post-on-sleep = <20>;
-		};
-
-		qcom,panel-supply-entry@1 {
-			reg = <1>;
-			qcom,supply-name = "vdd";
-			qcom,supply-min-voltage = <3000000>;
-			qcom,supply-max-voltage = <3000000>;
-			qcom,supply-enable-load = <30000>;
-			qcom,supply-disable-load = <0>;
-			qcom,supply-post-on-sleep = <0>;
-		};
-
-		qcom,panel-supply-entry@2 {
-			reg = <2>;
-			qcom,supply-name = "lab";
-			qcom,supply-min-voltage = <4600000>;
-			qcom,supply-max-voltage = <6000000>;
-			qcom,supply-enable-load = <0>;
-			qcom,supply-disable-load = <0>;
-		};
-
-		qcom,panel-supply-entry@3 {
-			reg = <3>;
-			qcom,supply-name = "ibb";
-			qcom,supply-min-voltage = <4600000>;
-			qcom,supply-max-voltage = <6000000>;
-			qcom,supply-enable-load = <0>;
-			qcom,supply-disable-load = <0>;
-			qcom,supply-post-on-sleep = <20>;
-		};
-	};
-
-	sde_dsi: qcom,dsi-display-primary {
-		compatible = "qcom,dsi-display";
-		label = "primary";
-
-		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
-		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
-
-		clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
-				 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
-				 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
-				 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
-				 <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
-				 <&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
-				 <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
-				 <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
-				 <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
-				 <&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
-				 <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
-				 <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
-				 <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
-				 <&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
-				 <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
-				 <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
-		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
-				"cphy_byte_clk0", "cphy_pixel_clk0",
-				"src_byte_clk0", "src_pixel_clk0",
-				"shadow_byte_clk0", "shadow_pixel_clk0",
-				"mux_byte_clk1", "mux_pixel_clk1",
-				"cphy_byte_clk1", "cphy_pixel_clk1",
-				"src_byte_clk1", "src_pixel_clk1",
-				"shadow_byte_clk1", "shadow_pixel_clk1";
-
-		pinctrl-names = "panel_active", "panel_suspend";
-		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
-		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
-
-		qcom,platform-te-gpio = <&tlmm 82 0>;
-		qcom,panel-te-source = <0>;
-
-		vddio-supply = <&L12C>;
-		vdd-supply = <&L13C>;
-		lab-supply = <&ab_vreg>;
-		ibb-supply = <&ibb_vreg>;
-
-		qcom,mdp = <&mdss_mdp>;
-	};
-
-	sde_dsi1: qcom,dsi-display-secondary {
-		compatible = "qcom,dsi-display";
-		label = "secondary";
-
-		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
-		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
-
-		clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
-			 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
-			 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
-			 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
-			 <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
-			 <&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
-			 <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
-			 <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
-		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
-				"cphy_byte_clk0", "cphy_pixel_clk0",
-				"mux_byte_clk1", "mux_pixel_clk1",
-				"cphy_byte_clk1", "cphy_pixel_clk1";
-
-		pinctrl-names = "panel_active", "panel_suspend";
-		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
-		pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
-
-		qcom,platform-te-gpio = <&tlmm 83 0>;
-		qcom,panel-te-source = <1>;
-
-		vddio-supply = <&L12C>;
-		vdd-supply = <&L13C>;
-
-		qcom,mdp = <&mdss_mdp>;
-	};
-
 	sde_wb: qcom,wb-display@0 {
 		compatible = "qcom,wb-display";
 		cell-index = <0>;
@@ -136,6 +8,71 @@
 	};
 };
 
+&sde_dsi {
+	clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
+		 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
+		 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
+		 <&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
+		 <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
+		 <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
+		 <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
+		 <&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
+		 <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
+		 <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
+	clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+			"cphy_byte_clk0", "cphy_pixel_clk0",
+			"src_byte_clk0", "src_pixel_clk0",
+			"shadow_byte_clk0", "shadow_pixel_clk0",
+			"mux_byte_clk1", "mux_pixel_clk1",
+			"cphy_byte_clk1", "cphy_pixel_clk1",
+			"src_byte_clk1", "src_pixel_clk1",
+			"shadow_byte_clk1", "shadow_pixel_clk1";
+
+	pinctrl-names = "panel_active", "panel_suspend";
+	pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+	pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+	qcom,platform-te-gpio = <&tlmm 82 0>;
+	qcom,panel-te-source = <0>;
+
+	vddio-supply = <&L12C>;
+	vdd-supply = <&L13C>;
+	lab-supply = <&ab_vreg>;
+	ibb-supply = <&ibb_vreg>;
+};
+
+&sde_dsi1 {
+	clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
+		 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
+		 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
+		 <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
+		 <&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
+		 <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
+		 <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
+	clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+			"cphy_byte_clk0", "cphy_pixel_clk0",
+			"mux_byte_clk1", "mux_pixel_clk1",
+			"cphy_byte_clk1", "cphy_pixel_clk1";
+
+	pinctrl-names = "panel_active", "panel_suspend";
+	pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
+	pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
+
+	qcom,platform-te-gpio = <&tlmm 83 0>;
+	qcom,panel-te-source = <1>;
+
+	vddio-supply = <&L12C>;
+	vdd-supply = <&L13C>;
+};
+
+
 &mdss_mdp {
 	connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi
 		&sde_dsi1>;
@@ -148,20 +85,6 @@
 	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
 	qcom,mdss-dsi-panel-status-value = <0x1c>;
 	qcom,mdss-dsi-panel-status-read-length = <1>;
-	qcom,dsi-supported-dfps-list = <120 90 60 48>;
-	qcom,mdss-dsi-pan-enable-dynamic-fps;
-	qcom,mdss-dsi-min-refresh-rate = <48>;
-	qcom,mdss-dsi-max-refresh-rate = <120>;
-	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
-	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
-	qcom,mdss-dsi-display-timings {
-		timing@0 {
-			qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08
-				08 05 02 04 00 17 0c];
-			qcom,display-topology = <2 2 1>;
-			qcom,default-topology-index = <0>;
-		};
-	};
 };
 
 &dsi_r66451_amoled_60hz_video {
@@ -171,15 +94,6 @@
 	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
 	qcom,mdss-dsi-panel-status-value = <0x1c>;
 	qcom,mdss-dsi-panel-status-read-length = <1>;
-	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
-	qcom,mdss-dsi-display-timings {
-		timing@0 {
-			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04
-				04 03 02 04 00 0e 09];
-			qcom,display-topology = <2 2 1>;
-			qcom,default-topology-index = <0>;
-		};
-	};
 };
 
 &dsi_r66451_amoled_cmd {
@@ -189,41 +103,4 @@
 	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
 	qcom,mdss-dsi-panel-status-value = <0x1c>;
 	qcom,mdss-dsi-panel-status-read-length = <1>;
-	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
-	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
-	qcom,mdss-dsi-display-timings {
-		timing@0 {
-			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
-				04 03 02 04 00 0e 09];
-			qcom,display-topology = <2 2 1>;
-			qcom,default-topology-index = <0>;
-		};
-
-		timing@1 {
-			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
-				06 06 02 04 00 14 0a];
-			qcom,display-topology = <2 2 1>;
-			qcom,default-topology-index = <0>;
-		};
-
-		timing@2 {
-			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
-				07 08 02 04 00 19 0c];
-			qcom,display-topology = <2 2 1>;
-			qcom,default-topology-index = <0>;
-		};
-	};
-};
-
-&dsi_sim_vid {
-	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
-	qcom,mdss-dsi-display-timings {
-		timing@0 {
-			qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
-				01 01 02 04 00 06 06];
-			qcom,display-topology = <1 0 1>,
-						<2 0 1>;
-			qcom,default-topology-index = <0>;
-		};
-	};
 };