diff --git a/drivers/gpu/msm/kgsl_rgmu.c b/drivers/gpu/msm/kgsl_rgmu.c
index d62c18aa1db2..a4d96ce4cb65 100644
--- a/drivers/gpu/msm/kgsl_rgmu.c
+++ b/drivers/gpu/msm/kgsl_rgmu.c
@@ -163,7 +163,7 @@ static int rgmu_enable_clks(struct kgsl_device *device)
 	}
 
 	ret = clk_set_rate(rgmu->gpu_clk,
-		rgmu->gpu_freqs[pwr->default_pwrlevel]);
+		pwr->pwrlevels[pwr->default_pwrlevel].gpu_freq);
 	if (ret) {
 		dev_err(&rgmu->pdev->dev, "Couldn't set the GPU clock\n");
 		return ret;
@@ -276,9 +276,8 @@ static int rgmu_probe(struct kgsl_device *device, struct device_node *node)
 {
 	struct rgmu_device *rgmu;
 	struct platform_device *pdev = of_find_device_by_node(node);
-	struct kgsl_pwrctrl *pwr = &device->pwrctrl;
 	struct resource *res;
-	int i, ret = -ENXIO;
+	int ret = -ENXIO;
 
 	rgmu = devm_kzalloc(&pdev->dev, sizeof(*rgmu), GFP_KERNEL);
 
@@ -337,12 +336,6 @@ static int rgmu_probe(struct kgsl_device *device, struct device_node *node)
 	disable_irq(rgmu->rgmu_interrupt_num);
 	disable_irq(rgmu->oob_interrupt_num);
 
-	/* Retrieves GPU power level configurations */
-	for (i = 0; i < pwr->num_pwrlevels; i++)
-		rgmu->gpu_freqs[i] = pwr->pwrlevels[i].gpu_freq;
-
-	rgmu->num_gpupwrlevels = pwr->num_pwrlevels;
-
 	/* Set up RGMU idle states */
 	if (ADRENO_FEATURE(ADRENO_DEVICE(device), ADRENO_IFPC))
 		rgmu->idle_level = GPU_HW_IFPC;
@@ -425,7 +418,8 @@ static int rgmu_dcvs_set(struct kgsl_device *device,
 	if (pwrlevel == INVALID_DCVS_IDX)
 		return -EINVAL;
 
-	ret = clk_set_rate(rgmu->gpu_clk, rgmu->gpu_freqs[pwrlevel]);
+	ret = clk_set_rate(rgmu->gpu_clk,
+		device->pwrctrl.pwrlevels[pwrlevel].gpu_freq);
 	if (ret)
 		dev_err(&rgmu->pdev->dev, "Couldn't set the GPU clock\n");
 
diff --git a/drivers/gpu/msm/kgsl_rgmu.h b/drivers/gpu/msm/kgsl_rgmu.h
index eebd6c1de5d5..4b8f7f45955e 100644
--- a/drivers/gpu/msm/kgsl_rgmu.h
+++ b/drivers/gpu/msm/kgsl_rgmu.h
@@ -30,8 +30,6 @@
  * @clks: RGMU clocks including the GPU
  * @gpu_clk: Pointer to GPU core clock
  * @rgmu_clk: Pointer to rgmu clock
- * @gpu_freqs: GPU frequency table with lowest freq at index 0
- * @num_gpupwrlevels: number GPU frequencies in GPU freq table
  * @flags: RGMU flags
  * @idle_level: Minimal GPU idle power level
  * @fault_count: RGMU fault count
@@ -50,8 +48,6 @@ struct rgmu_device {
 	struct clk *clks[MAX_RGMU_CLKS];
 	struct clk *gpu_clk;
 	struct clk *rgmu_clk;
-	unsigned int gpu_freqs[MAX_GX_LEVELS];
-	unsigned int num_gpupwrlevels;
 	unsigned int idle_level;
 	unsigned int fault_count;
 };