From 8bbe2b36c39726cbb6ad6dc68afa71878a6ab084 Mon Sep 17 00:00:00 2001
From: weiweij <weiweij@lenovo.com>
Date: Fri, 19 Nov 2021 10:23:44 +0800
Subject: [PATCH] pinctrl: distinguish reserve gpio list by macro definition

For each project has its own reserve gpio list. So we should have
the way to distinguish it in every different products.
We use a macro definition for this. If the gpios are not assigned to
TZ, they should be removed from the list.

Change-Id: I0837a3abdf8d7398aa2e7138563cb891b9f53780
Reviewed-on: https://gerrit.mot.com/2121376
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
---
 arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config | 1 +
 drivers/pinctrl/qcom/Kconfig                                 | 3 +++
 drivers/pinctrl/qcom/Makefile                                | 2 ++
 drivers/pinctrl/qcom/pinctrl-blair.c                         | 4 ++++
 4 files changed, 10 insertions(+)

diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config
index 8348c8dec1ca..2459a902c68a 100644
--- a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config
+++ b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config
@@ -21,3 +21,4 @@ CONFIG_ZRAM_WRITEBACK=y
 # CONFIG_REGULATOR_QPNP_LCDB is not set
 CONFIG_AW882XX_STEREO_SMARTPA=y
 # CONFIG_MICRON_UFSHID is not set
+CONFIG_QUP0_SE2_AP=y
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d20e59378909..e374c49d01e2 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -343,4 +343,7 @@ config PINCTRL_BLAIR
 	  Say Y here to compile statically, or M here to compile it as a module.
 	  If unsure, say N.
 
+config QUP0_SE2_AP
+        bool "Set GPIO of QUP0_SE2 as AP side"
+
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 1ba4ba27a173..24ad4cb8a9f7 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 # Qualcomm pin control drivers
+ccflags-$(CONFIG_QUP0_SE2_AP)	+= -DQUP0_SE2_AP
+
 obj-$(CONFIG_PINCTRL_MSM)	+= pinctrl-msm.o
 obj-$(CONFIG_PINCTRL_APQ8064)	+= pinctrl-apq8064.o
 obj-$(CONFIG_PINCTRL_APQ8084)	+= pinctrl-apq8084.o
diff --git a/drivers/pinctrl/qcom/pinctrl-blair.c b/drivers/pinctrl/qcom/pinctrl-blair.c
index 43f4a7660198..648e457c3974 100644
--- a/drivers/pinctrl/qcom/pinctrl-blair.c
+++ b/drivers/pinctrl/qcom/pinctrl-blair.c
@@ -1593,7 +1593,11 @@ static const struct msm_pingroup blair_groups[] = {
 };
 
 static const int blair_reserved_gpios[] = {
+#ifdef QUP0_SE2_AP
 	13, 14, 15, 16, -1
+#else
+	13, 14, 15, 16, 45, 46, 56, 57, -1
+#endif
 };
 
 static const struct msm_gpio_wakeirq_map blair_mpm_map[] = {