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- New Device Support

Browse source 
- New Clocksource driver from ST
    - New MFD/ACPI/DMA drivers for Intel's Sunrisepoint PCH based platforms
    - Add support for Arizona WM8998 and WM1814
    - Add support for Dialog Semi DA9062 and DA9063
    - Add support for Kontron COMe-bBL6 and COMe-cBW6
    - Add support for X-Powers AXP152
    - Add support for Atmel, many
    - Add support for STMPE, many
    - Add support for USB in X-Powers AXP22X
 
  - Core Frameworks
    - New Base API to traverse devices and their children in reverse order
 
  - Bug Fixes
    - Fix race between runtime-suspend and IRQs
    - Obtain platform data form more reliable source
 
  - Fix-ups
    - Constifying things
    - Variable signage changes
    - Kconfig depends|selects changes
    - Make use of BIT() macro
    - Do not supply .owner attribute in *_driver structures
    - MAINTAINERS entries
    - Stop using set_irq_flags()
    - Start using irq_set_chained_handler_and_data()
    - Export DT device ID structures
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Merge tag 'mfd-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "New Device Support:
   - New Clocksource driver from ST
   - New MFD/ACPI/DMA drivers for Intel's Sunrisepoint PCH based platforms
   - Add support for Arizona WM8998 and WM1814
   - Add support for Dialog Semi DA9062 and DA9063
   - Add support for Kontron COMe-bBL6 and COMe-cBW6
   - Add support for X-Powers AXP152
   - Add support for Atmel, many
   - Add support for STMPE, many
   - Add support for USB in X-Powers AXP22X

  Core Frameworks:
   - New Base API to traverse devices and their children in reverse order

  Bug Fixes:
   - Fix race between runtime-suspend and IRQs
   - Obtain platform data form more reliable source

  Fix-ups:
   - Constifying things
   - Variable signage changes
   - Kconfig depends|selects changes
   - Make use of BIT() macro
   - Do not supply .owner attribute in *_driver structures
   - MAINTAINERS entries
   - Stop using set_irq_flags()
   - Start using irq_set_chained_handler_and_data()
   - Export DT device ID structures"

* tag 'mfd-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (69 commits)
  mfd: jz4740-adc: Init mask cache in generic IRQ chip
  mfd: cros_ec: spi: Add OF match table
  mfd: stmpe: Add OF match table
  mfd: max77686: Split out regulator part from the DT binding
  mfd: Add DT binding for Maxim MAX77802 IC
  mfd: max77686: Use a generic name for the PMIC node in the example
  mfd: max77686: Don't suggest in binding to use a deprecated property
  mfd: Add MFD_CROS_EC dependencies
  mfd: cros_ec: Remove CROS_EC_PROTO dependency for SPI and I2C drivers
  mfd: axp20x: Add a cell for the usb power_supply part of the axp20x PMICs
  mfd: axp20x: Add missing registers, and mark more registers volatile
  mfd: arizona: Fixup some formatting/white space errors
  mfd: wm8994: Fix NULL pointer exception on missing pdata
  of: Add vendor prefix for Nuvoton
  mfd: mt6397: Implement wake handler and suspend/resume to handle wake up event
  mfd: atmel-hlcdc: Add support for new SoCs
  mfd: Export OF module alias information in missing drivers
  mfd: stw481x: Export I2C module alias information
  mfd: da9062: Support for the DA9063 OnKey in the DA9062 core
  mfd: max899x: Avoid redundant irq_data lookup
  ...
This commit is contained in:
Linus Torvalds 2015-09-04 11:35:03 -07:00
commit 8bd8fd0a29
125 changed files with 4816 additions and 581 deletions
Download patch file Download diff file Expand all files Collapse all files

162
include/linux/mfd/88pm80x.h
View file

@ -60,60 +60,60 @@ enum {
/* page 0 basic: slave adder 0x60 */
#define PM800_STATUS_1 (0x01)
#define PM800_ONKEY_STS1 (1 << 0)
#define PM800_EXTON_STS1 (1 << 1)
#define PM800_CHG_STS1 (1 << 2)
#define PM800_BAT_STS1 (1 << 3)
#define PM800_VBUS_STS1 (1 << 4)
#define PM800_LDO_PGOOD_STS1 (1 << 5)
#define PM800_BUCK_PGOOD_STS1 (1 << 6)
#define PM800_ONKEY_STS1 BIT(0)
#define PM800_EXTON_STS1 BIT(1)
#define PM800_CHG_STS1 BIT(2)
#define PM800_BAT_STS1 BIT(3)
#define PM800_VBUS_STS1 BIT(4)
#define PM800_LDO_PGOOD_STS1 BIT(5)
#define PM800_BUCK_PGOOD_STS1 BIT(6)
#define PM800_STATUS_2 (0x02)
#define PM800_RTC_ALARM_STS2 (1 << 0)
#define PM800_RTC_ALARM_STS2 BIT(0)
/* Wakeup Registers */
#define PM800_WAKEUP1 (0x0D)
#define PM800_WAKEUP1 (0x0D)
#define PM800_WAKEUP2 (0x0E)
#define PM800_WAKEUP2_INV_INT (1 << 0)
#define PM800_WAKEUP2_INT_CLEAR (1 << 1)
#define PM800_WAKEUP2_INT_MASK (1 << 2)
#define PM800_WAKEUP2 (0x0E)
#define PM800_WAKEUP2_INV_INT BIT(0)
#define PM800_WAKEUP2_INT_CLEAR BIT(1)
#define PM800_WAKEUP2_INT_MASK BIT(2)
#define PM800_POWER_UP_LOG (0x10)
#define PM800_POWER_UP_LOG (0x10)
/* Referance and low power registers */
#define PM800_LOW_POWER1 (0x20)
#define PM800_LOW_POWER2 (0x21)
#define PM800_LOW_POWER_CONFIG3 (0x22)
#define PM800_LOW_POWER_CONFIG4 (0x23)
#define PM800_LOW_POWER_CONFIG3 (0x22)
#define PM800_LOW_POWER_CONFIG4 (0x23)
/* GPIO register */
#define PM800_GPIO_0_1_CNTRL (0x30)
#define PM800_GPIO0_VAL (1 << 0)
#define PM800_GPIO0_VAL BIT(0)
#define PM800_GPIO0_GPIO_MODE(x) (x << 1)
#define PM800_GPIO1_VAL (1 << 4)
#define PM800_GPIO1_VAL BIT(4)
#define PM800_GPIO1_GPIO_MODE(x) (x << 5)
#define PM800_GPIO_2_3_CNTRL (0x31)
#define PM800_GPIO2_VAL (1 << 0)
#define PM800_GPIO2_VAL BIT(0)
#define PM800_GPIO2_GPIO_MODE(x) (x << 1)
#define PM800_GPIO3_VAL (1 << 4)
#define PM800_GPIO3_VAL BIT(4)
#define PM800_GPIO3_GPIO_MODE(x) (x << 5)
#define PM800_GPIO3_MODE_MASK 0x1F
#define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
#define PM800_GPIO_4_CNTRL (0x32)
#define PM800_GPIO4_VAL (1 << 0)
#define PM800_GPIO_4_CNTRL (0x32)
#define PM800_GPIO4_VAL BIT(0)
#define PM800_GPIO4_GPIO_MODE(x) (x << 1)
#define PM800_HEADSET_CNTRL (0x38)
#define PM800_HEADSET_DET_EN (1 << 7)
#define PM800_HSDET_SLP (1 << 1)
#define PM800_HEADSET_DET_EN BIT(7)
#define PM800_HSDET_SLP BIT(1)
/* PWM register */
#define PM800_PWM1 (0x40)
#define PM800_PWM2 (0x41)
#define PM800_PWM3 (0x42)
#define PM800_PWM4 (0x43)
#define PM800_PWM1 (0x40)
#define PM800_PWM2 (0x41)
#define PM800_PWM3 (0x42)
#define PM800_PWM4 (0x43)
/* RTC Registers */
#define PM800_RTC_CONTROL (0xD0)
@ -123,55 +123,55 @@ enum {
#define PM800_RTC_MISC4 (0xE4)
#define PM800_RTC_MISC5 (0xE7)
/* bit definitions of RTC Register 1 (0xD0) */
#define PM800_ALARM1_EN (1 << 0)
#define PM800_ALARM_WAKEUP (1 << 4)
#define PM800_ALARM (1 << 5)
#define PM800_RTC1_USE_XO (1 << 7)
#define PM800_ALARM1_EN BIT(0)
#define PM800_ALARM_WAKEUP BIT(4)
#define PM800_ALARM BIT(5)
#define PM800_RTC1_USE_XO BIT(7)
/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
/* buck registers */
#define PM800_SLEEP_BUCK1 (0x30)
#define PM800_SLEEP_BUCK1 (0x30)
/* BUCK Sleep Mode Register 1: BUCK[1..4] */
#define PM800_BUCK_SLP1 (0x5A)
#define PM800_BUCK1_SLP1_SHIFT 0
#define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
#define PM800_BUCK_SLP1 (0x5A)
#define PM800_BUCK1_SLP1_SHIFT 0
#define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
/* page 2 GPADC: slave adder 0x02 */
#define PM800_GPADC_MEAS_EN1 (0x01)
#define PM800_MEAS_EN1_VBAT (1 << 2)
#define PM800_MEAS_EN1_VBAT BIT(2)
#define PM800_GPADC_MEAS_EN2 (0x02)
#define PM800_MEAS_EN2_RFTMP (1 << 0)
#define PM800_MEAS_GP0_EN (1 << 2)
#define PM800_MEAS_GP1_EN (1 << 3)
#define PM800_MEAS_GP2_EN (1 << 4)
#define PM800_MEAS_GP3_EN (1 << 5)
#define PM800_MEAS_GP4_EN (1 << 6)
#define PM800_MEAS_EN2_RFTMP BIT(0)
#define PM800_MEAS_GP0_EN BIT(2)
#define PM800_MEAS_GP1_EN BIT(3)
#define PM800_MEAS_GP2_EN BIT(4)
#define PM800_MEAS_GP3_EN BIT(5)
#define PM800_MEAS_GP4_EN BIT(6)
#define PM800_GPADC_MISC_CONFIG1 (0x05)
#define PM800_GPADC_MISC_CONFIG2 (0x06)
#define PM800_GPADC_MISC_GPFSM_EN (1 << 0)
#define PM800_GPADC_MISC_GPFSM_EN BIT(0)
#define PM800_GPADC_SLOW_MODE(x) (x << 3)
#define PM800_GPADC_MISC_CONFIG3 (0x09)
#define PM800_GPADC_MISC_CONFIG4 (0x0A)
#define PM800_GPADC_MISC_CONFIG3 (0x09)
#define PM800_GPADC_MISC_CONFIG4 (0x0A)
#define PM800_GPADC_PREBIAS1 (0x0F)
#define PM800_GPADC_PREBIAS1 (0x0F)
#define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
#define PM800_GPADC_PREBIAS2 (0x10)
#define PM800_GPADC_PREBIAS2 (0x10)
#define PM800_GP_BIAS_ENA1 (0x14)
#define PM800_GPADC_GP_BIAS_EN0 (1 << 0)
#define PM800_GPADC_GP_BIAS_EN1 (1 << 1)
#define PM800_GPADC_GP_BIAS_EN2 (1 << 2)
#define PM800_GPADC_GP_BIAS_EN3 (1 << 3)
#define PM800_GP_BIAS_ENA1 (0x14)
#define PM800_GPADC_GP_BIAS_EN0 BIT(0)
#define PM800_GPADC_GP_BIAS_EN1 BIT(1)
#define PM800_GPADC_GP_BIAS_EN2 BIT(2)
#define PM800_GPADC_GP_BIAS_EN3 BIT(3)
#define PM800_GP_BIAS_OUT1 (0x15)
#define PM800_BIAS_OUT_GP0 (1 << 0)
#define PM800_BIAS_OUT_GP1 (1 << 1)
#define PM800_BIAS_OUT_GP2 (1 << 2)
#define PM800_BIAS_OUT_GP3 (1 << 3)
#define PM800_BIAS_OUT_GP0 BIT(0)
#define PM800_BIAS_OUT_GP1 BIT(1)
#define PM800_BIAS_OUT_GP2 BIT(2)
#define PM800_BIAS_OUT_GP3 BIT(3)
#define PM800_GPADC0_LOW_TH 0x20
#define PM800_GPADC1_LOW_TH 0x21
@ -222,37 +222,37 @@ enum {
#define PM805_INT_STATUS1 (0x03)
#define PM805_INT1_HP1_SHRT (1 << 0)
#define PM805_INT1_HP2_SHRT (1 << 1)
#define PM805_INT1_MIC_CONFLICT (1 << 2)
#define PM805_INT1_CLIP_FAULT (1 << 3)
#define PM805_INT1_LDO_OFF (1 << 4)
#define PM805_INT1_SRC_DPLL_LOCK (1 << 5)
#define PM805_INT1_HP1_SHRT BIT(0)
#define PM805_INT1_HP2_SHRT BIT(1)
#define PM805_INT1_MIC_CONFLICT BIT(2)
#define PM805_INT1_CLIP_FAULT BIT(3)
#define PM805_INT1_LDO_OFF BIT(4)
#define PM805_INT1_SRC_DPLL_LOCK BIT(5)
#define PM805_INT_STATUS2 (0x04)
#define PM805_INT2_MIC_DET (1 << 0)
#define PM805_INT2_SHRT_BTN_DET (1 << 1)
#define PM805_INT2_VOLM_BTN_DET (1 << 2)
#define PM805_INT2_VOLP_BTN_DET (1 << 3)
#define PM805_INT2_RAW_PLL_FAULT (1 << 4)
#define PM805_INT2_FINE_PLL_FAULT (1 << 5)
#define PM805_INT2_MIC_DET BIT(0)
#define PM805_INT2_SHRT_BTN_DET BIT(1)
#define PM805_INT2_VOLM_BTN_DET BIT(2)
#define PM805_INT2_VOLP_BTN_DET BIT(3)
#define PM805_INT2_RAW_PLL_FAULT BIT(4)
#define PM805_INT2_FINE_PLL_FAULT BIT(5)
#define PM805_INT_MASK1 (0x05)
#define PM805_INT_MASK2 (0x06)
#define PM805_SHRT_BTN_DET (1 << 1)
#define PM805_SHRT_BTN_DET BIT(1)
/* number of status and int reg in a row */
#define PM805_INT_REG_NUM (2)
#define PM805_MIC_DET1 (0x07)
#define PM805_MIC_DET_EN_MIC_DET (1 << 0)
#define PM805_MIC_DET_EN_MIC_DET BIT(0)
#define PM805_MIC_DET2 (0x08)
#define PM805_MIC_DET_STATUS1 (0x09)
#define PM805_MIC_DET_STATUS1 (0x09)
#define PM805_MIC_DET_STATUS3 (0x0A)
#define PM805_AUTO_SEQ_STATUS1 (0x0B)
#define PM805_AUTO_SEQ_STATUS2 (0x0C)
#define PM805_MIC_DET_STATUS3 (0x0A)
#define PM805_AUTO_SEQ_STATUS1 (0x0B)
#define PM805_AUTO_SEQ_STATUS2 (0x0C)
#define PM805_ADC_SETTING1 (0x10)
#define PM805_ADC_SETTING2 (0x11)
@ -261,7 +261,7 @@ enum {
#define PM805_ADC_GAIN2 (0x13)
#define PM805_DMIC_SETTING (0x15)
#define PM805_DWS_SETTING (0x16)
#define PM805_MIC_CONFLICT_STS (0x17)
#define PM805_MIC_CONFLICT_STS (0x17)
#define PM805_PDM_SETTING1 (0x20)
#define PM805_PDM_SETTING2 (0x21)
@ -270,11 +270,11 @@ enum {
#define PM805_PDM_CONTROL2 (0x24)
#define PM805_PDM_CONTROL3 (0x25)
#define PM805_HEADPHONE_SETTING (0x26)
#define PM805_HEADPHONE_GAIN_A2A (0x27)
#define PM805_HEADPHONE_SHORT_STATE (0x28)
#define PM805_EARPHONE_SETTING (0x29)
#define PM805_AUTO_SEQ_SETTING (0x2A)
#define PM805_HEADPHONE_SETTING (0x26)
#define PM805_HEADPHONE_GAIN_A2A (0x27)
#define PM805_HEADPHONE_SHORT_STATE (0x28)
#define PM805_EARPHONE_SETTING (0x29)
#define PM805_AUTO_SEQ_SETTING (0x2A)
struct pm80x_rtc_pdata {
int vrtc;

3
include/linux/mfd/arizona/core.h
View file

@ -25,6 +25,8 @@ enum arizona_type {
WM5110 = 2,
WM8997 = 3,
WM8280 = 4,
WM8998 = 5,
WM1814 = 6,
};
#define ARIZONA_IRQ_GP1 0
@ -165,6 +167,7 @@ static inline int wm5102_patch(struct arizona *arizona)
int wm5110_patch(struct arizona *arizona);
int wm8997_patch(struct arizona *arizona);
int wm8998_patch(struct arizona *arizona);
extern int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop,
bool mandatory);

14
include/linux/mfd/arizona/pdata.h
View file

@ -101,7 +101,7 @@ struct arizona_pdata {
* useful for systems where and I2S bus with multiple data
* lines is mastered.
*/
int max_channels_clocked[ARIZONA_MAX_AIF];
unsigned int max_channels_clocked[ARIZONA_MAX_AIF];
/** GPIO5 is used for jack detection */
bool jd_gpio5;
@ -125,22 +125,22 @@ struct arizona_pdata {
unsigned int hpdet_channel;
/** Extra debounce timeout used during initial mic detection (ms) */
int micd_detect_debounce;
unsigned int micd_detect_debounce;
/** GPIO for mic detection polarity */
int micd_pol_gpio;
/** Mic detect ramp rate */
int micd_bias_start_time;
unsigned int micd_bias_start_time;
/** Mic detect sample rate */
int micd_rate;
unsigned int micd_rate;
/** Mic detect debounce level */
int micd_dbtime;
unsigned int micd_dbtime;
/** Mic detect timeout (ms) */
int micd_timeout;
unsigned int micd_timeout;
/** Force MICBIAS on for mic detect */
bool micd_force_micbias;
@ -162,6 +162,8 @@ struct arizona_pdata {
/**
* Mode of input structures
* One of the ARIZONA_INMODE_xxx values
* wm5102/wm5110/wm8280/wm8997: [0]=IN1 [1]=IN2 [2]=IN3 [3]=IN4
* wm8998: [0]=IN1A [1]=IN2A [2]=IN1B [3]=IN2B
*/
int inmode[ARIZONA_MAX_INPUT];

220
include/linux/mfd/arizona/registers.h
View file

@ -139,6 +139,7 @@
#define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7
#define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8
#define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9
#define ARIZONA_MIC_DETECT_4 0x2AB
#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
#define ARIZONA_ISOLATION_CONTROL 0x2CB
#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
@ -225,14 +226,18 @@
#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
#define ARIZONA_DRE_ENABLE 0x440
#define ARIZONA_DRE_CONTROL_1 0x441
#define ARIZONA_DRE_CONTROL_2 0x442
#define ARIZONA_DRE_CONTROL_3 0x443
#define ARIZONA_EDRE_ENABLE 0x448
#define ARIZONA_DAC_AEC_CONTROL_1 0x450
#define ARIZONA_DAC_AEC_CONTROL_2 0x451
#define ARIZONA_NOISE_GATE_CONTROL 0x458
#define ARIZONA_PDM_SPK1_CTRL_1 0x490
#define ARIZONA_PDM_SPK1_CTRL_2 0x491
#define ARIZONA_PDM_SPK2_CTRL_1 0x492
#define ARIZONA_PDM_SPK2_CTRL_2 0x493
#define ARIZONA_HP_TEST_CTRL_13 0x49A
#define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0
#define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1
#define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2
@ -310,6 +315,10 @@
#define ARIZONA_AIF3_TX_ENABLES 0x599
#define ARIZONA_AIF3_RX_ENABLES 0x59A
#define ARIZONA_AIF3_FORCE_WRITE 0x59B
#define ARIZONA_SPD1_TX_CONTROL 0x5C2
#define ARIZONA_SPD1_TX_CHANNEL_STATUS_1 0x5C3
#define ARIZONA_SPD1_TX_CHANNEL_STATUS_2 0x5C4
#define ARIZONA_SPD1_TX_CHANNEL_STATUS_3 0x5C5
#define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3
#define ARIZONA_SLIMBUS_RATES_1 0x5E5
#define ARIZONA_SLIMBUS_RATES_2 0x5E6
@ -643,6 +652,10 @@
#define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD
#define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE
#define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF
#define ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE 0x800
#define ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME 0x801
#define ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE 0x808
#define ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME 0x809
#define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880
#define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881
#define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882
@ -868,6 +881,7 @@
#define ARIZONA_GPIO5_CTRL 0xC04
#define ARIZONA_IRQ_CTRL_1 0xC0F
#define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10
#define ARIZONA_GP_SWITCH_1 0xC18
#define ARIZONA_MISC_PAD_CTRL_1 0xC20
#define ARIZONA_MISC_PAD_CTRL_2 0xC21
#define ARIZONA_MISC_PAD_CTRL_3 0xC22
@ -1169,6 +1183,13 @@
#define ARIZONA_DSP4_SCRATCH_1 0x1441
#define ARIZONA_DSP4_SCRATCH_2 0x1442
#define ARIZONA_DSP4_SCRATCH_3 0x1443
#define ARIZONA_FRF_COEFF_1 0x1700
#define ARIZONA_FRF_COEFF_2 0x1701
#define ARIZONA_FRF_COEFF_3 0x1702
#define ARIZONA_FRF_COEFF_4 0x1703
#define ARIZONA_V2_DAC_COMP_1 0x1704
#define ARIZONA_V2_DAC_COMP_2 0x1705
/*
* Field Definitions.
@ -2325,6 +2346,9 @@
#define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */
#define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */
#define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */
#define WM8998_HP_RATE_MASK 0x0006 /* HP_RATE - [2:1] */
#define WM8998_HP_RATE_SHIFT 1 /* HP_RATE - [2:1] */
#define WM8998_HP_RATE_WIDTH 2 /* HP_RATE - [2:1] */
#define ARIZONA_HP_RATE 0x0002 /* HP_RATE */
#define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */
#define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */
@ -2412,6 +2436,16 @@
#define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */
#define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */
/*
* R683 (0x2AB) - Mic Detect 4
*/
#define ARIZONA_MICDET_ADCVAL_DIFF_MASK 0xFF00 /* MICDET_ADCVAL_DIFF - [15:8] */
#define ARIZONA_MICDET_ADCVAL_DIFF_SHIFT 8 /* MICDET_ADCVAL_DIFF - [15:8] */
#define ARIZONA_MICDET_ADCVAL_DIFF_WIDTH 8 /* MICDET_ADCVAL_DIFF - [15:8] */
#define ARIZONA_MICDET_ADCVAL_MASK 0x007F /* MICDET_ADCVAL - [15:8] */
#define ARIZONA_MICDET_ADCVAL_SHIFT 0 /* MICDET_ADCVAL - [15:8] */
#define ARIZONA_MICDET_ADCVAL_WIDTH 7 /* MICDET_ADCVAL - [15:8] */
/*
* R707 (0x2C3) - Mic noise mix control 1
*/
@ -2528,6 +2562,12 @@
/*
* R785 (0x311) - ADC Digital Volume 1L
*/
#define ARIZONA_IN1L_SRC_MASK 0x4000 /* IN1L_SRC - [14] */
#define ARIZONA_IN1L_SRC_SHIFT 14 /* IN1L_SRC - [14] */
#define ARIZONA_IN1L_SRC_WIDTH 1 /* IN1L_SRC - [14] */
#define ARIZONA_IN1L_SRC_SE_MASK 0x2000 /* IN1L_SRC - [13] */
#define ARIZONA_IN1L_SRC_SE_SHIFT 13 /* IN1L_SRC - [13] */
#define ARIZONA_IN1L_SRC_SE_WIDTH 1 /* IN1L_SRC - [13] */
#define ARIZONA_IN_VU 0x0200 /* IN_VU */
#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
@ -2560,6 +2600,12 @@
/*
* R789 (0x315) - ADC Digital Volume 1R
*/
#define ARIZONA_IN1R_SRC_MASK 0x4000 /* IN1R_SRC - [14] */
#define ARIZONA_IN1R_SRC_SHIFT 14 /* IN1R_SRC - [14] */
#define ARIZONA_IN1R_SRC_WIDTH 1 /* IN1R_SRC - [14] */
#define ARIZONA_IN1R_SRC_SE_MASK 0x2000 /* IN1R_SRC - [13] */
#define ARIZONA_IN1R_SRC_SE_SHIFT 13 /* IN1R_SRC - [13] */
#define ARIZONA_IN1R_SRC_SE_WIDTH 1 /* IN1R_SRC - [13] */
#define ARIZONA_IN_VU 0x0200 /* IN_VU */
#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
@ -2604,6 +2650,12 @@
/*
* R793 (0x319) - ADC Digital Volume 2L
*/
#define ARIZONA_IN2L_SRC_MASK 0x4000 /* IN2L_SRC - [14] */
#define ARIZONA_IN2L_SRC_SHIFT 14 /* IN2L_SRC - [14] */
#define ARIZONA_IN2L_SRC_WIDTH 1 /* IN2L_SRC - [14] */
#define ARIZONA_IN2L_SRC_SE_MASK 0x2000 /* IN2L_SRC - [13] */
#define ARIZONA_IN2L_SRC_SE_SHIFT 13 /* IN2L_SRC - [13] */
#define ARIZONA_IN2L_SRC_SE_WIDTH 1 /* IN2L_SRC - [13] */
#define ARIZONA_IN_VU 0x0200 /* IN_VU */
#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
@ -3411,12 +3463,46 @@
#define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */
#define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
/*
* R1088 (0x440) - DRE Enable (WM8998)
*/
#define WM8998_DRE3L_ENA 0x0020 /* DRE3L_ENA */
#define WM8998_DRE3L_ENA_MASK 0x0020 /* DRE3L_ENA */
#define WM8998_DRE3L_ENA_SHIFT 5 /* DRE3L_ENA */
#define WM8998_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */
#define WM8998_DRE2L_ENA 0x0008 /* DRE2L_ENA */
#define WM8998_DRE2L_ENA_MASK 0x0008 /* DRE2L_ENA */
#define WM8998_DRE2L_ENA_SHIFT 3 /* DRE2L_ENA */
#define WM8998_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */
#define WM8998_DRE2R_ENA 0x0004 /* DRE2R_ENA */
#define WM8998_DRE2R_ENA_MASK 0x0004 /* DRE2R_ENA */
#define WM8998_DRE2R_ENA_SHIFT 2 /* DRE2R_ENA */
#define WM8998_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */
#define WM8998_DRE1L_ENA 0x0002 /* DRE1L_ENA */
#define WM8998_DRE1L_ENA_MASK 0x0002 /* DRE1L_ENA */
#define WM8998_DRE1L_ENA_SHIFT 1 /* DRE1L_ENA */
#define WM8998_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
#define WM8998_DRE1R_ENA 0x0001 /* DRE1R_ENA */
#define WM8998_DRE1R_ENA_MASK 0x0001 /* DRE1R_ENA */
#define WM8998_DRE1R_ENA_SHIFT 0 /* DRE1R_ENA */
#define WM8998_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */
/*
* R1089 (0x441) - DRE Control 1
*/
#define ARIZONA_DRE_ENV_TC_FAST_MASK 0x0F00 /* DRE_ENV_TC_FAST - [11:8] */
#define ARIZONA_DRE_ENV_TC_FAST_SHIFT 8 /* DRE_ENV_TC_FAST - [11:8] */
#define ARIZONA_DRE_ENV_TC_FAST_WIDTH 4 /* DRE_ENV_TC_FAST - [11:8] */
/*
* R1090 (0x442) - DRE Control 2
*/
#define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */
#define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */
#define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */
#define ARIZONA_DRE_ALOG_VOL_DELAY_MASK 0x000F /* DRE_ALOG_VOL_DELAY - [3:0] */
#define ARIZONA_DRE_ALOG_VOL_DELAY_SHIFT 0 /* DRE_ALOG_VOL_DELAY - [3:0] */
#define ARIZONA_DRE_ALOG_VOL_DELAY_WIDTH 4 /* DRE_ALOG_VOL_DELAY - [3:0] */
/*
* R1091 (0x443) - DRE Control 3
@ -3428,6 +3514,49 @@
#define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */
#define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */
/* R486 (0x448) - EDRE_Enable
*/
#define ARIZONA_EDRE_OUT4L_THR2_ENA 0x0200 /* EDRE_OUT4L_THR2_ENA */
#define ARIZONA_EDRE_OUT4L_THR2_ENA_MASK 0x0200 /* EDRE_OUT4L_THR2_ENA */
#define ARIZONA_EDRE_OUT4L_THR2_ENA_SHIFT 9 /* EDRE_OUT4L_THR2_ENA */
#define ARIZONA_EDRE_OUT4L_THR2_ENA_WIDTH 1 /* EDRE_OUT4L_THR2_ENA */
#define ARIZONA_EDRE_OUT4R_THR2_ENA 0x0100 /* EDRE_OUT4R_THR2_ENA */
#define ARIZONA_EDRE_OUT4R_THR2_ENA_MASK 0x0100 /* EDRE_OUT4R_THR2_ENA */
#define ARIZONA_EDRE_OUT4R_THR2_ENA_SHIFT 8 /* EDRE_OUT4R_THR2_ENA */
#define ARIZONA_EDRE_OUT4R_THR2_ENA_WIDTH 1 /* EDRE_OUT4R_THR2_ENA */
#define ARIZONA_EDRE_OUT4L_THR1_ENA 0x0080 /* EDRE_OUT4L_THR1_ENA */
#define ARIZONA_EDRE_OUT4L_THR1_ENA_MASK 0x0080 /* EDRE_OUT4L_THR1_ENA */
#define ARIZONA_EDRE_OUT4L_THR1_ENA_SHIFT 7 /* EDRE_OUT4L_THR1_ENA */
#define ARIZONA_EDRE_OUT4L_THR1_ENA_WIDTH 1 /* EDRE_OUT4L_THR1_ENA */
#define ARIZONA_EDRE_OUT4R_THR1_ENA 0x0040 /* EDRE_OUT4R_THR1_ENA */
#define ARIZONA_EDRE_OUT4R_THR1_ENA_MASK 0x0040 /* EDRE_OUT4R_THR1_ENA */
#define ARIZONA_EDRE_OUT4R_THR1_ENA_SHIFT 6 /* EDRE_OUT4R_THR1_ENA */
#define ARIZONA_EDRE_OUT4R_THR1_ENA_WIDTH 1 /* EDRE_OUT4R_THR1_ENA */
#define ARIZONA_EDRE_OUT3L_THR1_ENA 0x0020 /* EDRE_OUT3L_THR1_ENA */
#define ARIZONA_EDRE_OUT3L_THR1_ENA_MASK 0x0020 /* EDRE_OUT3L_THR1_ENA */
#define ARIZONA_EDRE_OUT3L_THR1_ENA_SHIFT 5 /* EDRE_OUT3L_THR1_ENA */
#define ARIZONA_EDRE_OUT3L_THR1_ENA_WIDTH 1 /* EDRE_OUT3L_THR1_ENA */
#define ARIZONA_EDRE_OUT3R_THR1_ENA 0x0010 /* EDRE_OUT3R_THR1_ENA */
#define ARIZONA_EDRE_OUT3R_THR1_ENA_MASK 0x0010 /* EDRE_OUT3R_THR1_ENA */
#define ARIZONA_EDRE_OUT3R_THR1_ENA_SHIFT 4 /* EDRE_OUT3R_THR1_ENA */
#define ARIZONA_EDRE_OUT3R_THR1_ENA_WIDTH 1 /* EDRE_OUT3R_THR1_ENA */
#define ARIZONA_EDRE_OUT2L_THR1_ENA 0x0008 /* EDRE_OUT2L_THR1_ENA */
#define ARIZONA_EDRE_OUT2L_THR1_ENA_MASK 0x0008 /* EDRE_OUT2L_THR1_ENA */
#define ARIZONA_EDRE_OUT2L_THR1_ENA_SHIFT 3 /* EDRE_OUT2L_THR1_ENA */
#define ARIZONA_EDRE_OUT2L_THR1_ENA_WIDTH 1 /* EDRE_OUT2L_THR1_ENA */
#define ARIZONA_EDRE_OUT2R_THR1_ENA 0x0004 /* EDRE_OUT2R_THR1_ENA */
#define ARIZONA_EDRE_OUT2R_THR1_ENA_MASK 0x0004 /* EDRE_OUT2R_THR1_ENA */
#define ARIZONA_EDRE_OUT2R_THR1_ENA_SHIFT 2 /* EDRE_OUT2R_THR1_ENA */
#define ARIZONA_EDRE_OUT2R_THR1_ENA_WIDTH 1 /* EDRE_OUT2R_THR1_ENA */
#define ARIZONA_EDRE_OUT1L_THR1_ENA 0x0002 /* EDRE_OUT1L_THR1_ENA */
#define ARIZONA_EDRE_OUT1L_THR1_ENA_MASK 0x0002 /* EDRE_OUT1L_THR1_ENA */
#define ARIZONA_EDRE_OUT1L_THR1_ENA_SHIFT 1 /* EDRE_OUT1L_THR1_ENA */
#define ARIZONA_EDRE_OUT1L_THR1_ENA_WIDTH 1 /* EDRE_OUT1L_THR1_ENA */
#define ARIZONA_EDRE_OUT1R_THR1_ENA 0x0001 /* EDRE_OUT1R_THR1_ENA */
#define ARIZONA_EDRE_OUT1R_THR1_ENA_MASK 0x0001 /* EDRE_OUT1R_THR1_ENA */
#define ARIZONA_EDRE_OUT1R_THR1_ENA_SHIFT 0 /* EDRE_OUT1R_THR1_ENA */
#define ARIZONA_EDRE_OUT1R_THR1_ENA_WIDTH 1 /* EDRE_OUT1R_THR1_ENA */
/*
* R1104 (0x450) - DAC AEC Control 1
*/
@ -4307,6 +4436,86 @@
#define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */
#define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */
/*
* R1474 (0x5C2) - SPD1 TX Control
*/
#define ARIZONA_SPD1_VAL2 0x2000 /* SPD1_VAL2 */
#define ARIZONA_SPD1_VAL2_MASK 0x2000 /* SPD1_VAL2 */
#define ARIZONA_SPD1_VAL2_SHIFT 13 /* SPD1_VAL2 */
#define ARIZONA_SPD1_VAL2_WIDTH 1 /* SPD1_VAL2 */
#define ARIZONA_SPD1_VAL1 0x1000 /* SPD1_VAL1 */
#define ARIZONA_SPD1_VAL1_MASK 0x1000 /* SPD1_VAL1 */
#define ARIZONA_SPD1_VAL1_SHIFT 12 /* SPD1_VAL1 */
#define ARIZONA_SPD1_VAL1_WIDTH 1 /* SPD1_VAL1 */
#define ARIZONA_SPD1_RATE_MASK 0x00F0 /* SPD1_RATE */
#define ARIZONA_SPD1_RATE_SHIFT 4 /* SPD1_RATE */
#define ARIZONA_SPD1_RATE_WIDTH 4 /* SPD1_RATE */
#define ARIZONA_SPD1_ENA 0x0001 /* SPD1_ENA */
#define ARIZONA_SPD1_ENA_MASK 0x0001 /* SPD1_ENA */
#define ARIZONA_SPD1_ENA_SHIFT 0 /* SPD1_ENA */
#define ARIZONA_SPD1_ENA_WIDTH 1 /* SPD1_ENA */
/*
* R1475 (0x5C3) - SPD1 TX Channel Status 1
*/
#define ARIZONA_SPD1_CATCODE_MASK 0xFF00 /* SPD1_CATCODE */
#define ARIZONA_SPD1_CATCODE_SHIFT 8 /* SPD1_CATCODE */
#define ARIZONA_SPD1_CATCODE_WIDTH 8 /* SPD1_CATCODE */
#define ARIZONA_SPD1_CHSTMODE_MASK 0x00C0 /* SPD1_CHSTMODE */
#define ARIZONA_SPD1_CHSTMODE_SHIFT 6 /* SPD1_CHSTMODE */
#define ARIZONA_SPD1_CHSTMODE_WIDTH 2 /* SPD1_CHSTMODE */
#define ARIZONA_SPD1_PREEMPH_MASK 0x0038 /* SPD1_PREEMPH */
#define ARIZONA_SPD1_PREEMPH_SHIFT 3 /* SPD1_PREEMPH */
#define ARIZONA_SPD1_PREEMPH_WIDTH 3 /* SPD1_PREEMPH */
#define ARIZONA_SPD1_NOCOPY 0x0004 /* SPD1_NOCOPY */
#define ARIZONA_SPD1_NOCOPY_MASK 0x0004 /* SPD1_NOCOPY */
#define ARIZONA_SPD1_NOCOPY_SHIFT 2 /* SPD1_NOCOPY */
#define ARIZONA_SPD1_NOCOPY_WIDTH 1 /* SPD1_NOCOPY */
#define ARIZONA_SPD1_NOAUDIO 0x0002 /* SPD1_NOAUDIO */
#define ARIZONA_SPD1_NOAUDIO_MASK 0x0002 /* SPD1_NOAUDIO */
#define ARIZONA_SPD1_NOAUDIO_SHIFT 1 /* SPD1_NOAUDIO */
#define ARIZONA_SPD1_NOAUDIO_WIDTH 1 /* SPD1_NOAUDIO */
#define ARIZONA_SPD1_PRO 0x0001 /* SPD1_PRO */
#define ARIZONA_SPD1_PRO_MASK 0x0001 /* SPD1_PRO */
#define ARIZONA_SPD1_PRO_SHIFT 0 /* SPD1_PRO */
#define ARIZONA_SPD1_PRO_WIDTH 1 /* SPD1_PRO */
/*
* R1475 (0x5C4) - SPD1 TX Channel Status 2
*/
#define ARIZONA_SPD1_FREQ_MASK 0xF000 /* SPD1_FREQ */
#define ARIZONA_SPD1_FREQ_SHIFT 12 /* SPD1_FREQ */
#define ARIZONA_SPD1_FREQ_WIDTH 4 /* SPD1_FREQ */
#define ARIZONA_SPD1_CHNUM2_MASK 0x0F00 /* SPD1_CHNUM2 */
#define ARIZONA_SPD1_CHNUM2_SHIFT 8 /* SPD1_CHNUM2 */
#define ARIZONA_SPD1_CHNUM2_WIDTH 4 /* SPD1_CHNUM2 */
#define ARIZONA_SPD1_CHNUM1_MASK 0x00F0 /* SPD1_CHNUM1 */
#define ARIZONA_SPD1_CHNUM1_SHIFT 4 /* SPD1_CHNUM1 */
#define ARIZONA_SPD1_CHNUM1_WIDTH 4 /* SPD1_CHNUM1 */
#define ARIZONA_SPD1_SRCNUM_MASK 0x000F /* SPD1_SRCNUM */
#define ARIZONA_SPD1_SRCNUM_SHIFT 0 /* SPD1_SRCNUM */
#define ARIZONA_SPD1_SRCNUM_WIDTH 4 /* SPD1_SRCNUM */
/*
* R1475 (0x5C5) - SPD1 TX Channel Status 3
*/
#define ARIZONA_SPD1_ORGSAMP_MASK 0x0F00 /* SPD1_ORGSAMP */
#define ARIZONA_SPD1_ORGSAMP_SHIFT 8 /* SPD1_ORGSAMP */
#define ARIZONA_SPD1_ORGSAMP_WIDTH 4 /* SPD1_ORGSAMP */
#define ARIZONA_SPD1_TXWL_MASK 0x00E0 /* SPD1_TXWL */
#define ARIZONA_SPD1_TXWL_SHIFT 5 /* SPD1_TXWL */
#define ARIZONA_SPD1_TXWL_WIDTH 3 /* SPD1_TXWL */
#define ARIZONA_SPD1_MAXWL 0x0010 /* SPD1_MAXWL */
#define ARIZONA_SPD1_MAXWL_MASK 0x0010 /* SPD1_MAXWL */
#define ARIZONA_SPD1_MAXWL_SHIFT 4 /* SPD1_MAXWL */
#define ARIZONA_SPD1_MAXWL_WIDTH 1 /* SPD1_MAXWL */
#define ARIZONA_SPD1_CS31_30_MASK 0x000C /* SPD1_CS31_30 */
#define ARIZONA_SPD1_CS31_30_SHIFT 2 /* SPD1_CS31_30 */
#define ARIZONA_SPD1_CS31_30_WIDTH 2 /* SPD1_CS31_30 */
#define ARIZONA_SPD1_CLKACU_MASK 0x0003 /* SPD1_CLKACU */
#define ARIZONA_SPD1_CLKACU_SHIFT 2 /* SPD1_CLKACU */
#define ARIZONA_SPD1_CLKACU_WIDTH 0 /* SPD1_CLKACU */
/*
* R1507 (0x5E3) - SLIMbus Framer Ref Gear
*/
@ -4561,6 +4770,13 @@
#define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */
#define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */
/*
* R3096 (0xC18) - GP Switch 1
*/
#define ARIZONA_SW1_MODE_MASK 0x0003 /* SW1_MODE - [1:0] */
#define ARIZONA_SW1_MODE_SHIFT 0 /* SW1_MODE - [1:0] */
#define ARIZONA_SW1_MODE_WIDTH 2 /* SW1_MODE - [1:0] */
/*
* R3104 (0xC20) - Misc Pad Ctrl 1
*/
@ -6301,6 +6517,10 @@
/*
* R3366 (0xD26) - Interrupt Raw Status 8
*/
#define ARIZONA_SPDIF_OVERCLOCKED_STS 0x8000 /* SPDIF_OVERCLOCKED_STS */
#define ARIZONA_SPDIF_OVERCLOCKED_STS_MASK 0x8000 /* SPDIF_OVERCLOCKED_STS */
#define ARIZONA_SPDIF_OVERCLOCKED_STS_SHIFT 15 /* SPDIF_OVERCLOCKED_STS */
#define ARIZONA_SPDIF_OVERCLOCKED_STS_WIDTH 1 /* SPDIF_OVERCLOCKED_STS */
#define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */
#define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */
#define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */

67
include/linux/mfd/axp20x.h
View file

@ -12,7 +12,8 @@
#define __LINUX_MFD_AXP20X_H
enum {
AXP202_ID = 0,
AXP152_ID = 0,
AXP202_ID,
AXP209_ID,
AXP221_ID,
AXP288_ID,
@ -22,6 +23,24 @@ enum {
#define AXP20X_DATACACHE(m) (0x04 + (m))
/* Power supply */
#define AXP152_PWR_OP_MODE 0x01
#define AXP152_LDO3456_DC1234_CTRL 0x12
#define AXP152_ALDO_OP_MODE 0x13
#define AXP152_LDO0_CTRL 0x15
#define AXP152_DCDC2_V_OUT 0x23
#define AXP152_DCDC2_V_SCAL 0x25
#define AXP152_DCDC1_V_OUT 0x26
#define AXP152_DCDC3_V_OUT 0x27
#define AXP152_ALDO12_V_OUT 0x28
#define AXP152_DLDO1_V_OUT 0x29
#define AXP152_DLDO2_V_OUT 0x2a
#define AXP152_DCDC4_V_OUT 0x2b
#define AXP152_V_OFF 0x31
#define AXP152_OFF_CTRL 0x32
#define AXP152_PEK_KEY 0x36
#define AXP152_DCDC_FREQ 0x37
#define AXP152_DCDC_MODE 0x80
#define AXP20X_PWR_INPUT_STATUS 0x00
#define AXP20X_PWR_OP_MODE 0x01
#define AXP20X_USB_OTG_STATUS 0x02
@ -69,6 +88,13 @@ enum {
#define AXP22X_CHRG_CTRL3 0x35
/* Interrupt */
#define AXP152_IRQ1_EN 0x40
#define AXP152_IRQ2_EN 0x41
#define AXP152_IRQ3_EN 0x42
#define AXP152_IRQ1_STATE 0x48
#define AXP152_IRQ2_STATE 0x49
#define AXP152_IRQ3_STATE 0x4a
#define AXP20X_IRQ1_EN 0x40
#define AXP20X_IRQ2_EN 0x41
#define AXP20X_IRQ3_EN 0x42
@ -127,6 +153,19 @@ enum {
#define AXP22X_PWREN_CTRL2 0x8d
/* GPIO */
#define AXP152_GPIO0_CTRL 0x90
#define AXP152_GPIO1_CTRL 0x91
#define AXP152_GPIO2_CTRL 0x92
#define AXP152_GPIO3_CTRL 0x93
#define AXP152_LDOGPIO2_V_OUT 0x96
#define AXP152_GPIO_INPUT 0x97
#define AXP152_PWM0_FREQ_X 0x98
#define AXP152_PWM0_FREQ_Y 0x99
#define AXP152_PWM0_DUTY_CYCLE 0x9a
#define AXP152_PWM1_FREQ_X 0x9b
#define AXP152_PWM1_FREQ_Y 0x9c
#define AXP152_PWM1_DUTY_CYCLE 0x9d
#define AXP20X_GPIO0_CTRL 0x90
#define AXP20X_LDO5_V_OUT 0x91
#define AXP20X_GPIO1_CTRL 0x92
@ -151,6 +190,12 @@ enum {
#define AXP20X_CC_CTRL 0xb8
#define AXP20X_FG_RES 0xb9
/* OCV */
#define AXP20X_RDC_H 0xba
#define AXP20X_RDC_L 0xbb
#define AXP20X_OCV(m) (0xc0 + (m))
#define AXP20X_OCV_MAX 0xf
/* AXP22X specific registers */
#define AXP22X_BATLOW_THRES1 0xe6
@ -217,6 +262,26 @@ enum {
};
/* IRQs */
enum {
AXP152_IRQ_LDO0IN_CONNECT = 1,
AXP152_IRQ_LDO0IN_REMOVAL,
AXP152_IRQ_ALDO0IN_CONNECT,
AXP152_IRQ_ALDO0IN_REMOVAL,
AXP152_IRQ_DCDC1_V_LOW,
AXP152_IRQ_DCDC2_V_LOW,
AXP152_IRQ_DCDC3_V_LOW,
AXP152_IRQ_DCDC4_V_LOW,
AXP152_IRQ_PEK_SHORT,
AXP152_IRQ_PEK_LONG,
AXP152_IRQ_TIMER,
AXP152_IRQ_PEK_RIS_EDGE,
AXP152_IRQ_PEK_FAL_EDGE,
AXP152_IRQ_GPIO3_INPUT,
AXP152_IRQ_GPIO2_INPUT,
AXP152_IRQ_GPIO1_INPUT,
AXP152_IRQ_GPIO0_INPUT,
};
enum {
AXP20X_IRQ_ACIN_OVER_V = 1,
AXP20X_IRQ_ACIN_PLUGIN,

50
include/linux/mfd/da9062/core.h Normal file
View file

@ -0,0 +1,50 @@
/*
* Copyright (C) 2015 Dialog Semiconductor Ltd.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MFD_DA9062_CORE_H__
#define __MFD_DA9062_CORE_H__
#include <linux/interrupt.h>
#include <linux/mfd/da9062/registers.h>
/* Interrupts */
enum da9062_irqs {
/* IRQ A */
DA9062_IRQ_ONKEY,
DA9062_IRQ_ALARM,
DA9062_IRQ_TICK,
DA9062_IRQ_WDG_WARN,
DA9062_IRQ_SEQ_RDY,
/* IRQ B*/
DA9062_IRQ_TEMP,
DA9062_IRQ_LDO_LIM,
DA9062_IRQ_DVC_RDY,
DA9062_IRQ_VDD_WARN,
/* IRQ C */
DA9062_IRQ_GPI0,
DA9062_IRQ_GPI1,
DA9062_IRQ_GPI2,
DA9062_IRQ_GPI3,
DA9062_IRQ_GPI4,
DA9062_NUM_IRQ,
};
struct da9062 {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irq;
};
#endif /* __MFD_DA9062_CORE_H__ */

1108
include/linux/mfd/da9062/registers.h Normal file
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File diff suppressed because it is too large Load diff

1
include/linux/mfd/da9063/core.h
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@ -51,6 +51,7 @@ enum da9063_irqs {
DA9063_IRQ_COMP_1V2,
DA9063_IRQ_LDO_LIM,
DA9063_IRQ_REG_UVOV,
DA9063_IRQ_DVC_RDY,
DA9063_IRQ_VDD_MON,
DA9063_IRQ_WARN,
DA9063_IRQ_GPI0,

6
include/linux/mfd/lpc_ich.h
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@ -20,12 +20,6 @@
#ifndef LPC_ICH_H
#define LPC_ICH_H
/* Watchdog resources */
#define ICH_RES_IO_TCO 0
#define ICH_RES_IO_SMI 1
#define ICH_RES_MEM_OFF 2
#define ICH_RES_MEM_GCS_PMC 0
/* GPIO resources */
#define ICH_RES_GPIO 0
#define ICH_RES_GPE0 1

1
include/linux/mfd/mt6397/core.h
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@ -57,6 +57,7 @@ struct mt6397_chip {
int irq;
struct irq_domain *irq_domain;
struct mutex irqlock;
u16 wake_mask[2];
u16 irq_masks_cur[2];
u16 irq_masks_cache[2];
};

19
include/linux/platform_data/itco_wdt.h Normal file
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@ -0,0 +1,19 @@
/*
* Platform data for the Intel TCO Watchdog
*/
#ifndef _ITCO_WDT_H_
#define _ITCO_WDT_H_
/* Watchdog resources */
#define ICH_RES_IO_TCO 0
#define ICH_RES_IO_SMI 1
#define ICH_RES_MEM_OFF 2
#define ICH_RES_MEM_GCS_PMC 0
struct itco_wdt_platform_data {
char name[32];
unsigned int version;
};
#endif /* _ITCO_WDT_H_ */