From 8bea7d6100b58f49c32e631490054834bb57d9ca Mon Sep 17 00:00:00 2001
From: Lijuan Gao <lijuang@qti.qualcomm.com>
Date: Wed, 31 Mar 2021 14:50:14 +0800
Subject: [PATCH] ARM: dts: msm: Enable L1SS sleep for p-v2.1

PCIe0 phy on v2.1 manages the phy PLL properly hence
remove the software workaround to keep the phy PLL
always on.

Change-Id: I435a5776a75b6613d93f47d46ced65e0080b3a94
---
 qcom/lahainap-v2.1.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi
index 4b57547fab01..53307dcb647b 100644
--- a/qcom/lahainap-v2.1.dtsi
+++ b/qcom/lahainap-v2.1.dtsi
@@ -7,6 +7,7 @@
 };
 
 &pcie0 {
+	qcom,l1ss-sleep-disable = <0x0>;
 	qcom,pcie-phy-ver = <21101>;
 	qcom,phy-sequence = <0x0240 0x03 0x0
 			0x0094 0x08 0x0