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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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phy: qcom-ufs-qrbtc: Add ufs phy driver for presilicon
Add the phy driver used for presilicon verification of ufs. Change-Id: Ie7cceffd49eb24066e4a1bcf47b1f0c5115ce116 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This commit is contained in:
Asutosh Das
parent
e6f2727ba4
commit
8c4285997d
4 changed files with 349 additions and 0 deletions
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@ -66,6 +66,15 @@ config PHY_QCOM_UFS_20NM
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help
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Support for 20nm UFS QMP phy present on QCOM chipsets.
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config PHY_QCOM_UFS_QRBTC_SDM845
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tristate "Qualcomm Technologies, Inc. UFS Presil Phy Driver"
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depends on PHY_QCOM_UFS && REGULATOR_STUB
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help
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Enable this to support UFS PHY on pre-silicon platforms.
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The support is restricted to HS-G1 only on both Tx and Rx.
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No low power mode support is present.
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Doesn't restrict number of lanes.
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endif
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config PHY_QCOM_USB_HS
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@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o
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obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
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obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
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obj-$(CONFIG_PHY_QCOM_UFS_QRBTC_SDM845) += phy-qcom-ufs-qrbtc-sdm845.o
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158
drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c
Normal file
158
drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c
Normal file
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@ -0,0 +1,158 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "phy-qcom-ufs-qrbtc-sdm845.h"
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#define UFS_PHY_NAME "ufs_phy_qrbtc_sdm845"
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static
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int ufs_qcom_phy_qrbtc_sdm845_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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int err;
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int tbl_size_A, tbl_size_B;
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struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
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tbl_A = phy_cal_table_rate_A;
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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tbl_B = phy_cal_table_rate_B;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy,
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tbl_A, tbl_size_A,
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tbl_B, tbl_size_B,
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is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev,
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"%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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return err;
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}
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static int
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ufs_qcom_phy_qrbtc_sdm845_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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/*
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* The value we are polling for is 0x3D which represents the
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* following masks:
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* RESET_SM field: 0x5
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* RESTRIMDONE bit: BIT(3)
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* PLLLOCK bit: BIT(4)
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* READY bit: BIT(5)
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*/
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#define QSERDES_COM_RESET_SM_REG_POLL_VAL 0x3D
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err = readl_poll_timeout(phy_common->mmio + QSERDES_COM_RESET_SM,
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val, (val == QSERDES_COM_RESET_SM_REG_POLL_VAL), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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static void ufs_qcom_phy_qrbtc_sdm845_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 temp;
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writel_relaxed(0x01, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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temp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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temp |= 0x1;
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writel_relaxed(temp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qrbtc_sdm845_init(struct phy *generic_phy)
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{
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return 0;
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}
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static int ufs_qcom_phy_qrbtc_sdm845_exit(struct phy *generic_phy)
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{
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return 0;
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}
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static struct phy_ops ufs_qcom_phy_qrbtc_sdm845_phy_ops = {
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.init = ufs_qcom_phy_qrbtc_sdm845_init,
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.exit = ufs_qcom_phy_qrbtc_sdm845_exit,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_qrbtc_sdm845_ops = {
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.calibrate = ufs_qcom_phy_qrbtc_sdm845_phy_calibrate,
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.start_serdes = ufs_qcom_phy_qrbtc_sdm845_start_serdes,
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.is_physical_coding_sublayer_ready =
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ufs_qcom_phy_qrbtc_sdm845_is_pcs_ready,
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};
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static int ufs_qcom_phy_qrbtc_sdm845_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qrbtc_sdm845 *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qrbtc_sdm845_phy_ops, &phy_qrbtc_sdm845_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qrbtc_sdm845_of_match[] = {
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{.compatible = "qcom,ufs-phy-qrbtc-sdm845"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qrbtc_sdm845_of_match);
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static struct platform_driver ufs_qcom_phy_qrbtc_sdm845_driver = {
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.probe = ufs_qcom_phy_qrbtc_sdm845_probe,
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.driver = {
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.of_match_table = ufs_qcom_phy_qrbtc_sdm845_of_match,
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.name = "ufs_qcom_phy_qrbtc_sdm845",
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},
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};
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module_platform_driver(ufs_qcom_phy_qrbtc_sdm845_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QRBTC SDM845");
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MODULE_LICENSE("GPL v2");
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181
drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.h
Normal file
181
drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.h
Normal file
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@ -0,0 +1,181 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef UFS_QCOM_PHY_QRBTC_SDM845_H_
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#define UFS_QCOM_PHY_QRBTC_SDM845_H_
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#include "phy-qcom-ufs-i.h"
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/* QCOM UFS PHY control registers */
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#define COM_OFF(x) (0x000 + x)
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#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
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#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
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#define PHY_OFF(x) (0xC00 + x)
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#define PHY_USR(x) (x)
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/* UFS PHY PLL block registers */
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#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x00)
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#define QSERDES_COM_PLL_VCOTAIL_EN COM_OFF(0x04)
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#define QSERDES_COM_PLL_CNTRL COM_OFF(0x14)
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#define QSERDES_COM_PLL_IP_SETI COM_OFF(0x18)
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x20)
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#define QSERDES_COM_PLL_CP_SETI COM_OFF(0x24)
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#define QSERDES_COM_PLL_IP_SETP COM_OFF(0x28)
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#define QSERDES_COM_PLL_CP_SETP COM_OFF(0x2C)
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#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x38)
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#define QSERDES_COM_RES_CODE_TXBAND COM_OFF(0x3C)
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#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x40)
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#define QSERDES_COM_PLLLOCK_CMP1 COM_OFF(0x44)
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#define QSERDES_COM_PLLLOCK_CMP2 COM_OFF(0x48)
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#define QSERDES_COM_PLLLOCK_CMP3 COM_OFF(0x4C)
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#define QSERDES_COM_PLLLOCK_CMP_EN COM_OFF(0x50)
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#define QSERDES_COM_DEC_START1 COM_OFF(0x64)
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#define QSERDES_COM_DIV_FRAC_START1 COM_OFF(0x98)
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#define QSERDES_COM_DIV_FRAC_START2 COM_OFF(0x9C)
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#define QSERDES_COM_DIV_FRAC_START3 COM_OFF(0xA0)
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#define QSERDES_COM_DEC_START2 COM_OFF(0xA4)
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#define QSERDES_COM_PLL_RXTXEPCLK_EN COM_OFF(0xA8)
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#define QSERDES_COM_PLL_CRCTRL COM_OFF(0xAC)
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#define QSERDES_COM_PLL_CLKEPDIV COM_OFF(0xB0)
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#define QSERDES_COM_RESET_SM COM_OFF(0xBC)
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/* TX LANE n (0, 1) registers */
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#define QSERDES_TX_CLKBUF_ENABLE(n) TX_OFF(n, 0x4)
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/* RX LANE n (0, 1) registers */
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#define QSERDES_RX_CDR_CONTROL(n) RX_OFF(n, 0x0)
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#define QSERDES_RX_RX_IQ_RXDET_EN(n) RX_OFF(n, 0x28)
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#define QSERDES_RX_SIGDET_CNTRL(n) RX_OFF(n, 0x34)
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#define QSERDES_RX_RX_BAND(n) RX_OFF(n, 0x38)
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#define QSERDES_RX_CDR_CONTROL_HALF(n) RX_OFF(n, 0x98)
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#define QSERDES_RX_CDR_CONTROL_QUARTER(n) RX_OFF(n, 0x9C)
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#define QSERDES_RX_PWM_CNTRL1(n) RX_OFF(n, 0x80)
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#define QSERDES_RX_PWM_CNTRL2(n) RX_OFF(n, 0x84)
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#define QSERDES_RX_PWM_NDIV(n) RX_OFF(n, 0x88)
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#define QSERDES_RX_SIGDET_CNTRL2(n) RX_OFF(n, 0x8C)
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#define QSERDES_RX_UFS_CNTRL(n) RX_OFF(n, 0x90)
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/* UFS PHY registers */
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#define UFS_PHY_PHY_START PHY_OFF(0x00)
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#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
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#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x08)
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#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x0C)
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#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x134)
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#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1C4)
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/* QRBTC V2 USER REGISTERS */
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#define U11_UFS_RESET_REG_OFFSET PHY_USR(0x4)
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#define U11_QRBTC_CONTROL_OFFSET PHY_USR(0x18)
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#define U11_QRBTC_TX_CLK_CTRL PHY_USR(0x20)
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static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PHY_START, 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
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/* QSERDES Common */
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x03),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x16),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_TXBAND, 0xC0),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0x03),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x13),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0x43),
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/* QSERDES TX */
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/* Enable large amplitude setting */
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x29),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x29),
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/* QSERDES RX0 */
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x08),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL2(0), 0x40),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_NDIV(0), 0x30),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x40),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_BAND(0), 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0xF3),
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/* QSERDES RX1 */
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x08),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL2(1), 0x40),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_NDIV(1), 0x30),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x40),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_BAND(1), 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0xF3),
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/* QSERDES PLL Settings - Series A */
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xFF),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
|
||||
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
|
||||
/* QSERDES PLL Settings - Series B */
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* This structure represents the qrbtc-sdm845 specific phy.
|
||||
* common_cfg MUST remain the first field in this structure
|
||||
* in case extra fields are added. This way, when calling
|
||||
* get_ufs_qcom_phy() of generic phy, we can extract the
|
||||
* common phy structure (struct ufs_qcom_phy) out of it
|
||||
* regardless of the relevant specific phy.
|
||||
*/
|
||||
struct ufs_qcom_phy_qrbtc_sdm845 {
|
||||
struct ufs_qcom_phy common_cfg;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue