From 22f7eed317772064bf694c0895bc6661f7beb8d5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 27 Jan 2021 12:25:46 +0530 Subject: [PATCH] interconnect: qcom: Add qos configuration for scshrike Enable qos configuration for the interconnect nodes. Change-Id: Id841c208f9cdca6509fe20b1d846c7202286397e Signed-off-by: Veera Vegivada --- drivers/interconnect/qcom/scshrike.c | 655 ++++++++++++++++++++++++++- 1 file changed, 654 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/scshrike.c b/drivers/interconnect/qcom/scshrike.c index 721c44951b95..2fcd2d1513a4 100644 --- a/drivers/interconnect/qcom/scshrike.c +++ b/drivers/interconnect/qcom/scshrike.c @@ -1,10 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * */ #include +#include #include #include #include @@ -18,6 +19,7 @@ #include "icc-rpmh.h" #include "bcm-voter.h" +#include "qnoc-qos.h" static LIST_HEAD(qnoc_probe_list); static DEFINE_MUTEX(probe_list_lock); @@ -29,42 +31,91 @@ static struct qcom_icc_node qhm_a1noc_cfg = { .id = MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_A1NOC }, }; +static struct qcom_icc_qosbox xm_pcie3_0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xb000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", .id = MASTER_PCIE_0, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_pcie3_0_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; +static struct qcom_icc_qosbox xm_pcie3_1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x4000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", .id = MASTER_PCIE_1, .channels = 1, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_pcie3_1_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; +static struct qcom_icc_qosbox xm_pcie3_2_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x7000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_pcie3_2 = { .name = "xm_pcie3_2", .id = MASTER_PCIE_2, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_pcie3_2_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; +static struct qcom_icc_qosbox xm_pcie3_3_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x8000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_pcie3_3 = { .name = "xm_pcie3_3", .id = MASTER_PCIE_3, .channels = 1, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_pcie3_3_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; @@ -74,51 +125,112 @@ static struct qcom_icc_node xm_ufs_card = { .id = MASTER_UFS_CARD, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_ufs_g4_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xf000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_ufs_g4 = { .name = "xm_ufs_g4", .id = MASTER_UFS_GEN4, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_ufs_g4_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x3000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .id = MASTER_UFS_MEM, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_ufs_mem_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .id = MASTER_USB3_0, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_usb3_0_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_usb3_1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x5000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", .id = MASTER_USB3_1, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_usb3_1_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_usb3_2_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x9000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_usb3_2 = { .name = "xm_usb3_2", .id = MASTER_USB3_2, .channels = 1, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_usb3_2_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; @@ -128,114 +240,259 @@ static struct qcom_icc_node qhm_a2noc_cfg = { .id = MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_A2NOC }, }; +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x1b000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .id = MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qdss_bam_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qhm_qspi_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x12000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", .id = MASTER_QSPI_0, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qspi_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qhm_qspi1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x13000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node qhm_qspi1 = { .name = "qhm_qspi1", .id = MASTER_QSPI_1, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qspi1_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qhm_qup0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x9000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", .id = MASTER_QUP_0, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qup0_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qhm_qup1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x19000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", .id = MASTER_QUP_1, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qup1_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qhm_qup2_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x1a000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", .id = MASTER_QUP_2, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qup2_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qxm_crypto_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x7000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .id = MASTER_CRYPTO, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_crypto_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox qxm_ipa_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x8000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .id = MASTER_IPA, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_ipa_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_emac_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x10000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_emac = { .name = "xm_emac", .id = MASTER_EMAC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_emac_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_qdss_etr_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xd000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", .id = MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_qdss_etr_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_sdc2_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xe000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", .id = MASTER_SDCC_2, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_sdc2_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; +static struct qcom_icc_qosbox xm_sdc4_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xf000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", .id = MASTER_SDCC_4, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_sdc4_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; @@ -254,6 +511,7 @@ static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .id = MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_CAMNOC_UNCOMP }, }; @@ -263,6 +521,7 @@ static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .id = MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_CAMNOC_UNCOMP }, }; @@ -272,15 +531,28 @@ static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .id = MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_CAMNOC_UNCOMP }, }; +static struct qcom_icc_qosbox qnm_npu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x16000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", .id = MASTER_NPU, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_npu_qos, .num_links = 1, .links = { SLAVE_CDSP_MEM_NOC }, }; @@ -290,6 +562,7 @@ static struct qcom_icc_node qnm_snoc = { .id = MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 56, .links = { SLAVE_A1NOC_CFG, SLAVE_A2NOC_CFG, SLAVE_AHB2PHY_CENTER, SLAVE_AHB2PHY_EAST, @@ -326,34 +599,71 @@ static struct qcom_icc_node qhm_cnoc_dc_noc = { .id = MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 2, .links = { SLAVE_GEM_NOC_CFG, SLAVE_LLCC_CFG }, }; +static struct qcom_icc_qosbox acm_apps_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 8, + .offsets = { 0x30000, 0x30080, 0x30100, 0x30180, 0x30200, 0x30280, 0x30300, 0x30380 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node acm_apps = { .name = "acm_apps", .id = MASTER_APPSS_PROC, .channels = 4, .buswidth = 64, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &acm_apps_qos, .num_links = 3, .links = { SLAVE_ECC, SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; +static struct qcom_icc_qosbox acm_gpu_tcu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x30400 }, + .config = &(struct qos_config) { + .prio = 6, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node acm_gpu_tcu = { .name = "acm_gpu_tcu", .id = MASTER_GPU_TCU, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &acm_gpu_tcu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; +static struct qcom_icc_qosbox acm_sys_tcu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x30480 }, + .config = &(struct qos_config) { + .prio = 6, + .urg_fwd = 0, + }, +}; + static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", .id = MASTER_SYS_TCU, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &acm_sys_tcu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; @@ -363,80 +673,177 @@ static struct qcom_icc_node qhm_gemnoc_cfg = { .id = MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 3, .links = { SLAVE_MSS_PROC_MS_MPU_CFG, SLAVE_SERVICE_GEM_NOC, SLAVE_SERVICE_GEM_NOC_1 }, }; +static struct qcom_icc_qosbox qnm_cmpnoc_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x56400, 0x56480 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", .id = MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_cmpnoc_qos, .num_links = 3, .links = { SLAVE_ECC, SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qnm_gpu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 4, + .offsets = { 0x56500, 0x56580, 0x56600, 0x56680 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", .id = MASTER_GFX3D, .channels = 4, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_gpu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x56700, 0x56780 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .id = MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_mnoc_hf_qos, .num_links = 1, .links = { SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x30800 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .id = MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qnm_pcie_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x30880 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", .id = MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_pcie_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_SNOC, SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x56800 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .id = MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_snoc_gc_qos, .num_links = 1, .links = { SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x30980 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .id = MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_snoc_sf_qos, .num_links = 1, .links = { SLAVE_LLCC }, }; +static struct qcom_icc_qosbox qxm_ecc_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x60a00, 0x60a80 }, + .config = &(struct qos_config) { + .prio = 4, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_ecc = { .name = "qxm_ecc", .id = MASTER_ECC, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_ecc_qos, .num_links = 1, .links = { SLAVE_LLCC }, }; @@ -446,6 +853,7 @@ static struct qcom_icc_node ipa_core_master = { .id = MASTER_IPA_CORE, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_IPA_CORE }, }; @@ -455,6 +863,7 @@ static struct qcom_icc_node llcc_mc = { .id = MASTER_LLCC, .channels = 8, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_EBI1 }, }; @@ -464,87 +873,196 @@ static struct qcom_icc_node qhm_mnoc_cfg = { .id = MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_MNOC }, }; +static struct qcom_icc_qosbox qxm_camnoc_hf0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", .id = MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_camnoc_hf0_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_camnoc_hf1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xb000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", .id = MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_camnoc_hf1_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x9000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", .id = MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_camnoc_sf_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_mdp0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xc000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", .id = MASTER_MDP0, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_mdp0_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_mdp1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xd000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", .id = MASTER_MDP1, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_mdp1_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_rot_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xe000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", .id = MASTER_ROTATOR, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_rot_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_venus0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xf000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", .id = MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_venus0_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_venus1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x10000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", .id = MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_venus1_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; +static struct qcom_icc_qosbox qxm_venus_arm9_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x11000 }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", .id = MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_venus_arm9_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; @@ -554,6 +1072,7 @@ static struct qcom_icc_node qhm_snoc_cfg = { .id = MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_SNOC }, }; @@ -563,6 +1082,7 @@ static struct qcom_icc_node qnm_aggre1_noc = { .id = MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 6, .links = { SLAVE_APPSS, SLAVE_SNOC_CNOC, SLAVE_SNOC_GEM_NOC_SF, SLAVE_IMEM, @@ -574,6 +1094,7 @@ static struct qcom_icc_node qnm_aggre2_noc = { .id = MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, .num_links = 11, .links = { SLAVE_APPSS, SLAVE_SNOC_CNOC, SLAVE_SNOC_GEM_NOC_SF, SLAVE_IMEM, @@ -588,26 +1109,51 @@ static struct qcom_icc_node qnm_gemnoc = { .id = MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 6, .links = { SLAVE_APPSS, SLAVE_SNOC_CNOC, SLAVE_IMEM, SLAVE_PIMEM, SLAVE_QDSS_STM, SLAVE_TCU }, }; +static struct qcom_icc_qosbox qxm_pimem_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x14000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", .id = MASTER_PIMEM, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_pimem_qos, .num_links = 2, .links = { SLAVE_SNOC_GEM_NOC_GC, SLAVE_IMEM }, }; +static struct qcom_icc_qosbox xm_gic_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x11000 }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + static struct qcom_icc_node xm_gic = { .name = "xm_gic", .id = MASTER_GIC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_gic_qos, .num_links = 2, .links = { SLAVE_SNOC_GEM_NOC_GC, SLAVE_IMEM }, }; @@ -617,6 +1163,7 @@ static struct qcom_icc_node qnm_mnoc_hf_disp = { .id = MASTER_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_LLCC_DISP }, }; @@ -626,6 +1173,7 @@ static struct qcom_icc_node qnm_mnoc_sf_disp = { .id = MASTER_MNOC_SF_MEM_NOC_DISP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_LLCC_DISP }, }; @@ -635,6 +1183,7 @@ static struct qcom_icc_node llcc_mc_disp = { .id = MASTER_LLCC_DISP, .channels = 8, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_EBI1_DISP }, }; @@ -644,6 +1193,7 @@ static struct qcom_icc_node qxm_mdp0_disp = { .id = MASTER_MDP0_DISP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC_DISP }, }; @@ -653,6 +1203,7 @@ static struct qcom_icc_node qxm_mdp1_disp = { .id = MASTER_MDP1_DISP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC_DISP }, }; @@ -662,6 +1213,7 @@ static struct qcom_icc_node qxm_rot_disp = { .id = MASTER_ROTATOR_DISP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC_DISP }, }; @@ -671,6 +1223,7 @@ static struct qcom_icc_node qns_a1noc_snoc = { .id = SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A1NOC_SNOC }, }; @@ -680,6 +1233,7 @@ static struct qcom_icc_node qns_pcie_mem_noc = { .id = SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_GEM_NOC_PCIE_SNOC }, }; @@ -689,6 +1243,7 @@ static struct qcom_icc_node srvc_aggre1_noc = { .id = SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -697,6 +1252,7 @@ static struct qcom_icc_node qns_a2noc_snoc = { .id = SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A2NOC_SNOC }, }; @@ -706,6 +1262,7 @@ static struct qcom_icc_node srvc_aggre2_noc = { .id = SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -714,6 +1271,7 @@ static struct qcom_icc_node qns_camnoc_uncomp = { .id = SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -722,6 +1280,7 @@ static struct qcom_icc_node qns_cdsp_mem_noc = { .id = SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_COMPUTE_NOC }, }; @@ -731,6 +1290,7 @@ static struct qcom_icc_node qhs_a1_noc_cfg = { .id = SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A1NOC_CFG }, }; @@ -740,6 +1300,7 @@ static struct qcom_icc_node qhs_a2_noc_cfg = { .id = SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A2NOC_CFG }, }; @@ -749,6 +1310,7 @@ static struct qcom_icc_node qhs_ahb2phy_refgen_center = { .id = SLAVE_AHB2PHY_CENTER, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -757,6 +1319,7 @@ static struct qcom_icc_node qhs_ahb2phy_refgen_east = { .id = SLAVE_AHB2PHY_EAST, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -765,6 +1328,7 @@ static struct qcom_icc_node qhs_ahb2phy_refgen_west = { .id = SLAVE_AHB2PHY_WEST, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -773,6 +1337,7 @@ static struct qcom_icc_node qhs_ahb2phy_south = { .id = SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -781,6 +1346,7 @@ static struct qcom_icc_node qhs_aop = { .id = SLAVE_AOP, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -789,6 +1355,7 @@ static struct qcom_icc_node qhs_aoss = { .id = SLAVE_AOSS, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -797,6 +1364,7 @@ static struct qcom_icc_node qhs_camera_cfg = { .id = SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -805,6 +1373,7 @@ static struct qcom_icc_node qhs_clk_ctl = { .id = SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -813,6 +1382,7 @@ static struct qcom_icc_node qhs_compute_dsp = { .id = SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -821,6 +1391,7 @@ static struct qcom_icc_node qhs_cpr_cx = { .id = SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -829,6 +1400,7 @@ static struct qcom_icc_node qhs_cpr_mmcx = { .id = SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -837,6 +1409,7 @@ static struct qcom_icc_node qhs_cpr_mx = { .id = SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -845,6 +1418,7 @@ static struct qcom_icc_node qhs_crypto0_cfg = { .id = SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -853,6 +1427,7 @@ static struct qcom_icc_node qhs_ddrss_cfg = { .id = SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CNOC_DC_NOC }, }; @@ -862,6 +1437,7 @@ static struct qcom_icc_node qhs_display_cfg = { .id = SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -870,6 +1446,7 @@ static struct qcom_icc_node qhs_emac_cfg = { .id = SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -878,6 +1455,7 @@ static struct qcom_icc_node qhs_glm = { .id = SLAVE_GLM, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -886,6 +1464,7 @@ static struct qcom_icc_node qhs_gpuss_cfg = { .id = SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -894,6 +1473,7 @@ static struct qcom_icc_node qhs_imem_cfg = { .id = SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -902,6 +1482,7 @@ static struct qcom_icc_node qhs_ipa = { .id = SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -910,6 +1491,7 @@ static struct qcom_icc_node qhs_mnoc_cfg = { .id = SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CNOC_MNOC_CFG }, }; @@ -919,6 +1501,7 @@ static struct qcom_icc_node qhs_npu_cfg = { .id = SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -927,6 +1510,7 @@ static struct qcom_icc_node qhs_pcie0_cfg = { .id = SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -935,6 +1519,7 @@ static struct qcom_icc_node qhs_pcie1_cfg = { .id = SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -943,6 +1528,7 @@ static struct qcom_icc_node qhs_pcie2_cfg = { .id = SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -951,6 +1537,7 @@ static struct qcom_icc_node qhs_pcie3_cfg = { .id = SLAVE_PCIE_3_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -959,6 +1546,7 @@ static struct qcom_icc_node qhs_pdm = { .id = SLAVE_PDM, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -967,6 +1555,7 @@ static struct qcom_icc_node qhs_pimem_cfg = { .id = SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -975,6 +1564,7 @@ static struct qcom_icc_node qhs_prng = { .id = SLAVE_PRNG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -983,6 +1573,7 @@ static struct qcom_icc_node qhs_qdss_cfg = { .id = SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -991,6 +1582,7 @@ static struct qcom_icc_node qhs_qspi_0 = { .id = SLAVE_QSPI_0, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -999,6 +1591,7 @@ static struct qcom_icc_node qhs_qspi_1 = { .id = SLAVE_QSPI_1, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1007,6 +1600,7 @@ static struct qcom_icc_node qhs_qupv3_east0 = { .id = SLAVE_QUP_1, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1015,6 +1609,7 @@ static struct qcom_icc_node qhs_qupv3_east1 = { .id = SLAVE_QUP_2, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1023,6 +1618,7 @@ static struct qcom_icc_node qhs_qupv3_west = { .id = SLAVE_QUP_0, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1031,6 +1627,7 @@ static struct qcom_icc_node qhs_sdc2 = { .id = SLAVE_SDCC_2, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1039,6 +1636,7 @@ static struct qcom_icc_node qhs_sdc4 = { .id = SLAVE_SDCC_4, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1047,6 +1645,7 @@ static struct qcom_icc_node qhs_security = { .id = SLAVE_SECURITY, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1055,6 +1654,7 @@ static struct qcom_icc_node qhs_snoc_cfg = { .id = SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_CFG }, }; @@ -1064,6 +1664,7 @@ static struct qcom_icc_node qhs_spss_cfg = { .id = SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1072,6 +1673,7 @@ static struct qcom_icc_node qhs_tcsr = { .id = SLAVE_TCSR, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1080,6 +1682,7 @@ static struct qcom_icc_node qhs_tlmm_east = { .id = SLAVE_TLMM_EAST, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1088,6 +1691,7 @@ static struct qcom_icc_node qhs_tlmm_south = { .id = SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1096,6 +1700,7 @@ static struct qcom_icc_node qhs_tlmm_west = { .id = SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1104,6 +1709,7 @@ static struct qcom_icc_node qhs_tsif = { .id = SLAVE_TSIF, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1112,6 +1718,7 @@ static struct qcom_icc_node qhs_ufs_card_cfg = { .id = SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1120,6 +1727,7 @@ static struct qcom_icc_node qhs_ufs_mem0_cfg = { .id = SLAVE_UFS_MEM_0_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1128,6 +1736,7 @@ static struct qcom_icc_node qhs_ufs_mem1_cfg = { .id = SLAVE_UFS_MEM_1_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1136,6 +1745,7 @@ static struct qcom_icc_node qhs_usb3_0 = { .id = SLAVE_USB3_0, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1144,6 +1754,7 @@ static struct qcom_icc_node qhs_usb3_1 = { .id = SLAVE_USB3_1, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1152,6 +1763,7 @@ static struct qcom_icc_node qhs_usb3_2 = { .id = SLAVE_USB3_2, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1160,6 +1772,7 @@ static struct qcom_icc_node qhs_venus_cfg = { .id = SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1168,6 +1781,7 @@ static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .id = SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1176,6 +1790,7 @@ static struct qcom_icc_node srvc_cnoc = { .id = SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1184,6 +1799,7 @@ static struct qcom_icc_node qhs_gemnoc = { .id = SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_GEM_NOC_CFG }, }; @@ -1193,6 +1809,7 @@ static struct qcom_icc_node qhs_llcc = { .id = SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1201,6 +1818,7 @@ static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .id = SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1209,6 +1827,7 @@ static struct qcom_icc_node qns_ecc = { .id = SLAVE_ECC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1217,6 +1836,7 @@ static struct qcom_icc_node qns_gem_noc_snoc = { .id = SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_GEM_NOC_SNOC }, }; @@ -1226,6 +1846,7 @@ static struct qcom_icc_node qns_llcc = { .id = SLAVE_LLCC, .channels = 8, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LLCC }, }; @@ -1235,6 +1856,7 @@ static struct qcom_icc_node srvc_gemnoc = { .id = SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1243,6 +1865,7 @@ static struct qcom_icc_node srvc_gemnoc1 = { .id = SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1251,6 +1874,7 @@ static struct qcom_icc_node ipa_core_slave = { .id = SLAVE_IPA_CORE, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1259,6 +1883,7 @@ static struct qcom_icc_node ebi = { .id = SLAVE_EBI1, .channels = 8, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1267,6 +1892,7 @@ static struct qcom_icc_node qns2_mem_noc = { .id = SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_SF_MEM_NOC }, }; @@ -1276,6 +1902,7 @@ static struct qcom_icc_node qns_mem_noc_hf = { .id = SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_HF_MEM_NOC }, }; @@ -1285,6 +1912,7 @@ static struct qcom_icc_node srvc_mnoc = { .id = SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1293,6 +1921,7 @@ static struct qcom_icc_node qhs_apss = { .id = SLAVE_APPSS, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1301,6 +1930,7 @@ static struct qcom_icc_node qns_cnoc = { .id = SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_CNOC }, }; @@ -1310,6 +1940,7 @@ static struct qcom_icc_node qns_gemnoc_gc = { .id = SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_GC_MEM_NOC }, }; @@ -1319,6 +1950,7 @@ static struct qcom_icc_node qns_gemnoc_sf = { .id = SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_SF_MEM_NOC }, }; @@ -1328,6 +1960,7 @@ static struct qcom_icc_node qxs_imem = { .id = SLAVE_IMEM, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1336,6 +1969,7 @@ static struct qcom_icc_node qxs_pimem = { .id = SLAVE_PIMEM, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1344,6 +1978,7 @@ static struct qcom_icc_node srvc_snoc = { .id = SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1352,6 +1987,7 @@ static struct qcom_icc_node xs_pcie_0 = { .id = SLAVE_PCIE_0, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1360,6 +1996,7 @@ static struct qcom_icc_node xs_pcie_1 = { .id = SLAVE_PCIE_1, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1368,6 +2005,7 @@ static struct qcom_icc_node xs_pcie_2 = { .id = SLAVE_PCIE_2, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1376,6 +2014,7 @@ static struct qcom_icc_node xs_pcie_3 = { .id = SLAVE_PCIE_3, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1384,6 +2023,7 @@ static struct qcom_icc_node xs_qdss_stm = { .id = SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1392,6 +2032,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .id = SLAVE_TCU, .channels = 1, .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1400,6 +2041,7 @@ static struct qcom_icc_node qns_llcc_disp = { .id = SLAVE_LLCC_DISP, .channels = 8, .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LLCC_DISP }, }; @@ -1409,6 +2051,7 @@ static struct qcom_icc_node ebi_disp = { .id = SLAVE_EBI1_DISP, .channels = 8, .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; @@ -1417,6 +2060,7 @@ static struct qcom_icc_node qns2_mem_noc_disp = { .id = SLAVE_MNOC_SF_MEM_NOC_DISP, .channels = 1, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_SF_MEM_NOC_DISP }, }; @@ -1426,6 +2070,7 @@ static struct qcom_icc_node qns_mem_noc_hf_disp = { .id = SLAVE_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_HF_MEM_NOC_DISP }, }; @@ -2170,6 +2815,10 @@ static int qnoc_probe(struct platform_device *pdev) return ret; } + qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks); + if (qp->num_clks < 0) + return qp->num_clks; + for (i = 0; i < num_nodes; i++) { size_t j; @@ -2217,6 +2866,8 @@ err: icc_node_destroy(node->id); } + clk_bulk_put_all(qp->num_clks, qp->clks); + icc_provider_del(provider); return ret; } @@ -2232,6 +2883,8 @@ static int qnoc_remove(struct platform_device *pdev) icc_node_destroy(n->id); } + clk_bulk_put_all(qp->num_clks, qp->clks); + return icc_provider_del(provider); }