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Blackfin SPI Driver: ensure cache coherency before doing DMA
Flush or invalidate caches before doing DMA transfer, if needed. [Mike Frysinger <[email protected]>: add comment to address the issue "Full duplex only works for non-DMA transfers".] Signed-off-by: Vitja Makarov <[email protected]> Signed-off-by: Mike Frysinger <[email protected]> Signed-off-by: Bryan Wu <[email protected]> Cc: David Brownell <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
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1 changed files with 20 additions and 3 deletions
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@ -26,6 +26,10 @@
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#include <asm/portmux.h>
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#include <asm/bfin5xx_spi.h>
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/* reserved_mem_dcache_on and cache friends */
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#include <asm/cplbinit.h>
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#include <asm/cacheflush.h>
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#define DRV_NAME "bfin-spi"
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#define DRV_AUTHOR "Bryan Wu, Luke Yang"
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#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
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@ -738,9 +742,10 @@ static void pump_transfers(unsigned long data)
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width, transfer->len);
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/*
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* Try to map dma buffer and do a dma transfer if
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* successful use different way to r/w according to
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* drv_data->cur_chip->enable_dma
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* Try to map dma buffer and do a dma transfer. If successful use,
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* different way to r/w according to the enable_dma settings and if
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* we are not doing a full duplex transfer (since the hardware does
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* not support full duplex DMA transfers).
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*/
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if (!full_duplex && drv_data->cur_chip->enable_dma
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&& drv_data->len > 6) {
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@ -795,6 +800,12 @@ static void pump_transfers(unsigned long data)
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/* set transfer mode, and enable SPI */
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dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
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/* invalidate caches, if needed */
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if (bfin_addr_dcachable((unsigned long) drv_data->rx))
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invalidate_dcache_range((unsigned long) drv_data->rx,
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(unsigned long) (drv_data->rx +
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drv_data->len));
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/* clear tx reg soformer data is not shifted out */
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write_TDBR(drv_data, 0xFFFF);
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@ -815,6 +826,12 @@ static void pump_transfers(unsigned long data)
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} else if (drv_data->tx != NULL) {
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dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
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/* flush caches, if needed */
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if (bfin_addr_dcachable((unsigned long) drv_data->tx))
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flush_dcache_range((unsigned long) drv_data->tx,
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(unsigned long) (drv_data->tx +
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drv_data->len));
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/* start dma */
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dma_enable_irq(drv_data->dma_channel);
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dma_config = (RESTART | dma_width | DI_EN);
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